ICM7555 Datasheet by NXP USA Inc.

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1. General description
The ICM7555 is a CMOS timer providing significantly improved performance over the
standard NE/SE555 timer, while at the same time being a direct replacement for those
devices in most applications. Improved parameters include low supply current, wide
operating supply voltage range, low THRESHOLD, TRIGGER, and RESET currents, no
crowbarring of the supply current during output transitions, higher frequency performance
and no requirement to decouple CONTROL_VOLTAGE for stable operation.
The ICM7555 is a stable controller capable of producing accurate time delays or
frequencies.
In the one-shot mode, the pulse width of each circuit is precisely controlled by one
external resistor and capacitor. For astable operation as an oscillator, the free-running
frequency and the duty cycle are both accurately controlled by two external resistors and
one capacitor. Unlike the NE/SE555 device, the CONTROL_VOLTAGE terminal need not
be decoupled with a capacitor. The TRIGGER and RESET inputs are active LOW. The
output inverter can source or sink currents large enough to drive TTL loads or provide
minimal offsets to drive CMOS loads.
2. Features
nExact equivalent in most applications for NE/SE555
nLow supply current: 80 µA (typical)
nExtremely low trigger, threshold, and reset currents: 20 pA (typical)
nHigh-speed operation: 500 kHz guaranteed
nWide operating supply voltage range guaranteed 3 V to 16 V over full automotive
temperatures
nNormal reset function; no crowbarring of supply during output transition
nCan be used with higher-impedance timing elements than the NE/SE555 for longer
time constants
nTiming from microseconds through hours
nOperates in both astable and monostable modes
nAdjustable duty cycle
nHigh output source/sink driver can drive TTL/CMOS
nTypical temperature stability of 0.005 % / °C at 25 °C
nRail-to-rail outputs
ICM7555
General purpose CMOS timer
Rev. 02 — 3 August 2009 Product data sheet
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 2 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
3. Applications
nPrecision timing
nPulse generation
nSequential timing
nTime delay generation
nPulse width modulation
nPulse position modulation
nMissing pulse detector
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Temperature range Package
Name Description Version
ICM7555CD Tamb =0°C to +70 °C SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
ICM7555ID Tamb =40 °Cto+85°C
ICM7555CN Tamb =0°C to +70 °C DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
ICM7555IN Tamb =40 °Cto+85°C
Remark: Unused inputs should be connected to appropriate voltage from Table 3.
Fig 1. Functional diagram
002aae403
flip-flop
RESET
4
comparator A output
drivers
OUTPUT
3
N
DISCHARGE
GND
7
1
comparator B
R
R
R
GND
1
2
TRIGGER
CONTROL_VOLTAGE 5
THRESHOLD 6
VDD
8
jjjj jjjj
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 3 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
Refer to Figure 1 “Functional diagram”.
7.1 Function selection
[1] RESET will dominate all other inputs; TRIGGER will dominate over THRESHOLD.
Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for DIP8
VDD
DISCHARGE
THRESHOLD
CONTROL_VOLTAGE
GND
TRIGGER
OUTPUT
RESET
ICM7555CD
ICM7555ID
002aae400
1
2
3
4
6
5
8
7ICM7555CN
ICM7555IN
GND VDD
TRIGGER DISCHARGE
OUTPUT THRESHOLD
RESET CONTROL_VOLTAGE
002aae401
1
2
3
4
6
5
8
7
Table 2. Pin description
Symbol Pin Description
GND 1 supply ground
TRIGGER 2 start timer input; (active LOW)
OUTPUT 3 timer logic level output
RESET 4 timer inhibit input; (active LOW)
CONTROL_VOLTAGE 5 timing capacitor upper voltage sense input
THRESHOLD 6 timing capacitor lower voltage sense input
DISCHARGE 7 timing capacitor discharge output
VDD 8 supply voltage
Table 3. Function selection
THRESHOLD voltage TRIGGER voltage RESET[1] OUTPUT Discharge switch
don’t care don’t care L L on
>23V+ > 13V+ H L on
Vth <23V+ Vtrig >13V+ H stable stable
don’t care < 13V+ H H off
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 4 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
8. Limiting values
[1] Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater
than VDD + 0.3 V or less than GND 0.3 V may cause destructive latch-up. For this reason it is recommended that no inputs from
external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple
systems, the supply of the ICM7555 must be turned on first.
[2] Above 25 °C, derate at the following rates:
DIP8 package at 9.3 mW / °C
SO8 package at 6.2 mW / °C
[3] Refer to Section 11.2 “Power supply considerations” section.
9. Characteristics
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 18 V
VIinput voltage TRIGGER [1] 0.3 VDD + 0.3 V
CONTROL_VOLTAGE 0.3 VDD + 0.3 V
THRESHOLD 0.3 VDD + 0.3 V
RESET 0.3 VDD + 0.3 V
IOoutput current - 100 mA
P power dissipation Tamb =25°C (still air) [2][3]
DIP8 package - 1160 mW
SO8 package - 780 mW
Tstg storage temperature 65 +150 °C
Tsp solder point temperature soldering 60 s - 300 °C
Table 5. Characteristics
T
amb
=25
°
C unless otherwise specified.
Sym
bol Parameter Conditions Min Typ Max Unit
VDD supply voltage Tmin Tamb Tmax 3 - 16 V
IDD supply current[1] VDD =V
min - 50 200 µA
VDD =V
max - 180 300 µA
Astable mode timing[2][3]
f/f frequency stability - 1.0 5.0 %
f/V frequency variation with voltage - 0.1 3.0 %/V
f/T frequency variation with
temperature[4] VDD = 5 V - 50 - ppm/°C
VDD = 10 V - 75 - ppm/°C
VDD = 15 V - 100 - ppm/°C
VIinput voltage TRIGGER: VDD = 5 V 0.29VDD 0.31VDD 0.34VDD V
CONTROL_VOLTAGE: VDD = 5 V 0.62VDD 0.65VDD 0.67VDD V
THRESHOLD: VDD = 5 V 0.63VDD 0.65VDD 0.67VDD V
RESET: VDD =V
min and Vmax 0.4VDD 0.7VDD 1.0VDD V
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 5 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
[1] The supply current value is essentially independent of the TRIGGER, THRESHOLD and RESET voltages.
[2] Astable timing is calculated using the following equation:
The components are defined in Figure 15.
[3] RA, RB = 1 k to 100 k; C = 0.1 µF; 5 V < VDD <15V
[4] Parameter is not 100 % tested.
IIinput current TRIGGER
VDD =V
trig =V
max -50-pA
VDD =V
trig = 5 V - 10 - pA
VDD =V
trig =V
min -1-pA
THRESHOLD
VDD =V
th =V
max -50-pA
VDD =V
th =5V - 10 - pA
VDD =V
th =V
min -1-pA
RESET
VDD =V
rst =V
max - 100 - pA
VDD =V
rst =5V - 20 - pA
VDD =V
rst =V
min -2-pA
VOL LOW-level output voltage VDD =V
max; Isink = 3.2 mA - 0.1 0.4 V
VDD =5V; I
sink = 3.2 mA - 0.2 0.4 V
VOH HIGH-level output voltage Isource =1.0 mA
VDD =V
max 15.25 15.7 - V
VDD =5V
max 4.0 4.5 - V
Vooutput voltage DISCHARGE:
VDD =5V;I
DIS =10mA - 0.2 0.4 V
tr(o) output rise time[4] RL=10M; CL= 10 pF;
VDD =5V -4575ns
tf(o) output fall time[4] -2075ns
fosc oscillator frequency astable mode - - 500 kHz
Table 5. Characteristics
…continued
T
amb
=25
°
C unless otherwise specified.
Sym
bol Parameter Conditions Min Typ Max Unit
f1.38
RA2RB
+()C
---------------------------------
=
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 6 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
10. Typical performance curves
Fig 4. Supply current versus supply voltage
Tamb = +25 °C.
Fig 5. High output voltage drop versus output source current
Tamb = +25 °C.
Fig 6. Discharge low output voltage versus discharge sink current
VDD (V)
0 2015105
002aae404
100
150
50
200
250
IDD
(µA)
0
Tamb = 55 °C
+25 °C
+125 °C
002aae405
VDD VO (V)
101102
101
10
1
102
Io(source)
(mA)
101
VDD = 18 V
5 V
2 V
002aae406
VDIS (V)
101101
10
1
102
IDIS
(mA)
101
VDD = 18 V
5 V
2 V
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 7 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
a. Tamb = +125 °C.
b. Tamb = +25 °C.
c. Tamb = 55 °C.
Fig 7. Low output voltage versus output sink current
002aae407
VOL (V)
101101
10
1
102
Io(sink)
(mA)
101
VDD = 18 V
5 V
2 V
002aae408
VOL (V)
101101
10
1
102
Io(sink)
(mA)
101
VDD = 18 V
5 V
2 V
002aae409
VOL (V)
101101
10
1
102
Io(sink)
(mA)
101
VDD = 18 V
5 V
2 V
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 8 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
Fig 8. Minimum pulse width for triggering
Fig 9. Propagation delay versus voltage level of TRIGGER pulse (VDD = 5 V)
lowest voltage level of TRIGGER pulse (% VDD)
0 40302010
002aae410
200
300
100
400
500
0
TRIGGER pulse width (ns) VDD = 18 V
5 V
2 V
lowest voltage level of TRIGGER pulse (% VDD)
0 40302010
002aae411
0
750
500
250
1000
tPD
(ns) Tamb = 55 °C
+25 °C
+125 °C
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 9 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
Tamb = +25 °C
RA=R
B=10k
C = 0.1 µF
Fig 10. Normalized frequency stability as a function of supply voltage (astable mode)
RA=R
B=1k
C = 0.1 µF
Fig 11. Normalized frequency stability as a function of temperature (astable mode)
VDD (V)
0 2015105
002aae413
0
2
2
4
6
4
normalized frequency
(%)
Tamb (°C)
75 125752525
002aae414
4
2
0
2
4
normalized frequency
(%) VDD = 18 V
5 V
2 V
1 m _ m m mu m 1 Mn 10 Ms)
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 10 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
VDD =5V; T
amb = +25 °C
Fig 12. Free-running frequency as a function of RA, RB resistance and external
capacitance
VDD =5V; T
amb = +25 °C
Fig 13. Monostable time delay versus RA resistance and external capacitance
002aae415
102
C (µF)
105
f (Hz)
101107
104
106
105
104
103
102
101
103
102
101
1
10
1 k
10 k
100 k
1 M
10 M
002aae416
102
C (µF)
105
td (s)
10710
104
1101
102
103
104
105
106
103
102
101
1
10 1 k
10 k
100 k
1 M
10 M
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 11 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
11. Application information
11.1 General
The ICM7555 device is, in most instances, a direct replacement for the NE/SE555 device.
However, it is possible to effect economies in the external component count using the
ICM7555. Because the NE/SE555 device produces large crowbar currents in the output
driver, it is necessary to decouple the power supply lines with a good capacitor close to
the device. The ICM7555 device produces no such transients. See Figure 14.
The ICM7555 produces supply current spikes of only 2 mA to 3 mA instead of
300 mA to 400 mA and supply decoupling is normally not necessary. Secondly, in most
instances, the CONTROL_VOLTAGE decoupling capacitors are not required since the
input impedance of the CMOS comparators on chip are very high. Thus, for many
applications, 2 capacitors can be saved using an ICM7555.
11.2 Power supply considerations
Although the supply current consumed by the ICM7555 device is very low, the total
system supply can be high unless the timing components are high-impedance. Therefore,
high values for R and low values for C in Figure 15 and Figure 16 are recommended.
11.3 Output drive capability
The output driver consists of a CMOS inverter capable of driving most logic families
including CMOS and TTL. As such, if driving CMOS, the output swing at all supply
voltages will equal the supply voltage. At a supply voltage of 4.5 V or more, the ICM7555
will drive at least 2 standard TTL loads.
Tamb = +25 °C
(1) NE/SE555
(2) ICM7555
Fig 14. Supply current transient compared with a standard NE/SE555 device during an
output transition
100
300
500
IDD
(mA)
100
time (ns)
0 800600200 400
002aae417
(1)
(2)
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 12 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
11.4 Astable operation
If the circuit is connected as shown in Figure 15, it will trigger itself and free run as a
multivibrator. The external capacitor charges through RA and RB and discharges through
RBonly. Thus, the duty cycle (δ) may be precisely set by the ratio of these two resistors. In
this mode of operation, the capacitor charges and discharges between 13VDD and
23VDD. Since the charge rate and the threshold levels are directly proportional to the
supply voltage, the frequency of oscillation is independent of the supply voltage.
(1)
(2)
11.5 Monostable operation
In this mode of operation, the timer functions as a one-shot. Initially, the external
capacitor (C) is held discharged by a transistor inside the timer. Upon application of a
negative pulse to pin 2, TRIGGER, the internal flip-flop is set, which releases the
low-impedance on DISCHARGE; the external capacitor charges and drives the OUTPUT
HIGH. The voltage across the capacitor increases exponentially with a time constant
t=R
AC. When the voltage across the capacitor equals 23V+, the comparator resets the
flip-flop, which in turn discharges the capacitor rapidly and also drives the OUTPUT to its
LOW state. TRIGGER must return to a HIGH state before the OUTPUT can return to a
LOW state.
Fig 15. Astable operation
f1.38
RA2RB
+()C×
--------------------------------------
=
δRARB
+
RA2RB
+
-----------------------
=
GND
TRIGGER
OUTPUT
RESET
1
2
3
4
VDD
C
RB
RA
VDD
OUTPUT
DISCHARGE
THRESHOLD
CONTROL_VOLTAGE
VDD 8
7
6
5
VDD
002aae418
HJ
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 13 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
11.6 Control voltage
The CONTROL_VOLTAGE terminal permits the two trip voltages for the THRESHOLD
and TRIGGER internal comparators to be controlled. This provides the possibility of
oscillation frequency modulation in the astable mode, or even inhibition of oscillation,
depending on the applied voltage. In the monostable mode, delay times can be changed
by varying the applied voltage to the CONTROL_VOLTAGE pin.
11.7 RESET
The RESET terminal is designed to have essentially the same trip voltage as the standard
NE/SE555 device, i.e., 0.6 V to 0.7 V. At all supply voltages it represents an extremely
high input impedance. The mode of operation of the RESET function is, however, much
improved over the standard NE/SE555 device in that it controls only the internal flip-flop,
which in turn controls simultaneously the state of the OUTPUT and DISCHARGE pins.
This avoids the multiple threshold problems sometimes encountered with slow falling
edges in the NE/SE555 devices.
VDD 18 V; t = 1.05 RAC
Fig 16. Monostable operation
GND
TRIGGER
OUTPUT
RESET
1
2
3
4
DISCHARGE
THRESHOLD
CONTROL_VOLTAGE
VDD 8
7
6
5
VDD
002aae419
RA
optional
capacitor C
E© MWH
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 14 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
12. Package outline
Fig 17. Package outline SOT96-1 (SO8)
UNIT A
max. A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 5.0
4.8 4.0
3.8 1.27 6.2
5.8 1.05 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.10.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
1.0
0.4
SOT96-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
4
5
pin 1 index
1
8
y
076E03 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.20
0.19 0.16
0.15 0.05 0.244
0.228 0.028
0.024 0.028
0.012
0.010.010.041 0.004
0.039
0.016
0 2.5 5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
99-12-27
03-02-18
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 15 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
Fig 18. Package outline SOT97-1 (DIP8)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT97-1 99-12-27
03-02-13
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.14 0.53
0.38 0.36
0.23 9.8
9.2 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 1.154.2 0.51 3.2
inches 0.068
0.045 0.021
0.015 0.014
0.009
1.07
0.89
0.042
0.035 0.39
0.36 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0450.17 0.02 0.13
b2
050G01 MO-001 SC-504-8
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
8
1
5
4
b
E
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
pin 1 index
DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 16 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note
AN10365 “Surface mount reflow
soldering description”
.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
Solder bath specifications, including temperature and impurities
Tb
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 17 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
13.4 Reflow soldering
Key characteristics in reflow soldering are:
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a SnPb process, thus
reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 6 and 7
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 19.
Table 6. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 7. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
maxmum peak tempevaiure = MSL mun damage level mmmum peaklempevamve = mwnwmum samenng tempevahue
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 18 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
For further information on temperature profiles, refer to Application Note
AN10365
“Surface mount reflow soldering description”
.
14. Soldering of through-hole mount packages
14.1 Introduction to soldering through-hole mount packages
This text gives a very brief insight into wave, dip and manual soldering.
Wave soldering is the preferred method for mounting of through-hole mount IC packages
on a printed-circuit board.
14.2 Soldering by dipping or by solder wave
Driven by legislation and environmental forces the worldwide use of lead-free solder
pastes is increasing. Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb
or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
14.3 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.
MSL: Moisture Sensitivity Level
Fig 19. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 19 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
14.4 Package related soldering information
[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit
board.
[2] For PMFP packages hot bar soldering or manual soldering is suitable.
15. Abbreviations
Table 8. Suitability of through-hole mount IC packages for dipping and wave soldering
Package Soldering method
Dipping Wave
CPGA, HCPGA - suitable
DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable[1]
PMFP[2] - not suitable
Table 9. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductors
TTL Transistor-Transistor Logic
SCR Silicon-Controlled Rectifier
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 20 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
16. Revision history
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
ICM7555_2 20090803 Product data sheet - ICM7555_1
Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP
Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Provided separate pinning diagrams for SO8 and DIP8 packages (Figure 2 and Figure 3,
respectively).
Added Table 2 “Pin description”.
Table 4 “Limiting values”:
Symbols VTRIG, VCV, VTH, VRST are replaced with VI (specific pin names are now noted under
Conditions column).
Symbol/parameter “PDMAX, maximum power dissipation” replaced with “P, power dissipation” (only
maximum values given).
Symbol/parameter “TSTG, storage temperature range” replaced with “Tstg, storage temperature”.
Symbol changed from “TSOLD” to “Tsp, solder point temperature”
Table 5 “Characteristics”:
Symbols f/f, f/V, f/T, have been added for Astable mode timing.
Symbols VTRIG, VCV, VTH, VRST are replaced with VI (specific pin names are now noted under
Conditions column).
Symbols ITRIG, ITH, IRST are replaced with II (specific pin names are now noted under Conditions
column).
Symbol/parameter “VDIS, discharge output voltage” changed to “Vo, output voltage” (specific pin
name is now noted under Conditions column).
Symbol/parameter “tR, rise time of output” changed to “tr(o), output rise time”.
Symbol/parameter “tF, fall time of output” changed to “tf(o), output fall time”.
Symbol “FMAX” changed to “fosc, oscillator frequency”.
Section 11.4 “Astable operation”: changed symbol for duty cycle from “D” to “δ”.
Added Section 12 “Package outline”.
Added soldering information.
Added Section 15 “Abbreviations”.
ICM7555_1 19940831 Product specification ECN 853-1192 13721
dated 1994 Aug 31 -
ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 21 of 22
NXP Semiconductors ICM7555
General purpose CMOS timer
17. Legal information
17.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
founded by PHILIPS
NXP Semiconductors ICM7555
General purpose CMOS timer
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 August 2009
Document identifier: ICM7555_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
19. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
7.1 Function selection. . . . . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4
10 Typical performance curves . . . . . . . . . . . . . . . 6
11 Application information. . . . . . . . . . . . . . . . . . 11
11.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
11.2 Power supply considerations . . . . . . . . . . . . . 11
11.3 Output drive capability . . . . . . . . . . . . . . . . . . 11
11.4 Astable operation . . . . . . . . . . . . . . . . . . . . . . 12
11.5 Monostable operation . . . . . . . . . . . . . . . . . . . 12
11.6 Control voltage . . . . . . . . . . . . . . . . . . . . . . . . 13
11.7 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Soldering of SMD packages . . . . . . . . . . . . . . 16
13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 16
13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 16
13.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16
13.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 17
14 Soldering of through-hole mount packages . 18
14.1 Introduction to soldering through-hole mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
14.2 Soldering by dipping or by solder wave . . . . . 18
14.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 18
14.4 Package related soldering information . . . . . . 19
15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19
16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
18 Contact information. . . . . . . . . . . . . . . . . . . . . 21
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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