SIP11205 Datasheet by Vishay Siliconix

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— V VISHAY. 7‘: J TTT w Elli
Vishay Siliconix
SiP11205
Document Number: 69233
S-81795-Rev. C, 04-Aug-08
www.vishay.com
1
Product is End of Life 12/2014
Feed-Forward Controller with Primary MOSFET
Drivers for Intermediate Bus Converters
FEATURES
36 V to 75 V input voltage range
Withstand 100 V, 100 ms transient capability
Integrated ± 1.6 A typical high- and low-side MOSFET
drivers
Oscillator frequency is programmable from 200 kHz to
1 MHz (100 kHz to 500 kHz switching frequency) and can
be externally synchronized
Voltage feed-forward compensation
High voltage pre-regulator operates during start-up
Current sensing on primary low-side switch
Hiccup mode
System low input voltage detection
Chip UVLO function
Programmable soft-start function
Over temperature protection (160 °C)
Greater than 95.5 % efficiency for 42 V to 55 V input range
Better than 2 % line regulation at 9 A
APPLICATIONS
Intermediate bus architectures
Telecom and Datacom
Routers and servers
Storage area network
Base station
1/8 and 1/4 bricks
DESCRIPTION
SiP11205 is a feed-forward controller for the primary side of
a half-bridge intermediate bus converter (IBC). It is ideally
suited for isolated applications such as telecom, data
communications and other products requiring an IBC
architecture and conversion of standard bus voltages such
as 48 V to a lower intermediate voltage, where high
efficiency is required at low output voltages (24 V, 12 V, 9 V
or 5 V).
Designed to operate within the telecom voltage range of
36 V to 75 V and withstand 100 V transients for a period of
100 ms, the IC is designed for controlling and driving both
the low- and high-side switching devices of a half-bridge
converter.
The feed-forward feature is designed to make the converter
output semi-regulated and is beneficial for point-of-load
applications that require narrow input range. SiP11205 has
advanced current monitoring and control circuitry, which
allows the user to set the maximum current in the primary
circuit. This feature acts as protection against overcurrent
and output short circuit. Current sensing is by means of a
sense resistor connected in series with the primary low-side
MOSFET.
TYPICAL APPLICATION CIRCUIT
Si2303BDS
Si2303BDS
Si7456DP
Si7456DP
Si7848DP Si7848DP
Vo+
Vo-
42 V to 55 V
100 V/100 ms
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SiP11205
VINDET
VIN
VCC
COMP
CS
AGND
VREF
ROSC
BST
DH
LX
DL
PGND
SS
RDB
COSC
RDB2
RDB1
Vin+
Vin-
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Document Number: 69233
S-81795-Rev. C, 04-Aug-08
Vishay Siliconix
SiP11205
TECHNICAL DESCRIPTION
SiP11205 is a feed-forward controller on the primary side of
a half-bridge intermediate bus converter. With 100 V
depletion mode MOSFET in the chip, the SiP11205 is
capable of being powered directly from the high voltage bus
to VCC through an external PNP pass transistor, or may be
powered by an external supply directly to the VCC pin.
Without the use of an external pass transistor, failure of the
converter output to power VCC above the VREG level will
result in over temperature protection activating hiccup
operation whenever the pre-regulator power dissipation
becomes excessive.
The external high- and low-side N-Channel power MOSFETs
are driven by a built-in driver with ± 1.6 A peak current
capability. SiP11205 is available in the MLP44-16
PowerPAK® package and TSSOP-16 PowerPAK® package
and is specified over the ambient temperature range of
- 40 °C to 85 °C.
SIP11205 BLOCK DIAGRAM
Level
Shift
Pre Reg
Driver
Control
OSC
PWM Comp
+
-
Hi-side driver
Low-side driver
OTP
VIN V
CC
ROSC
VREF
PGND
SS
Ram
p
BST
DH
LX
DL
UVLO
Over Current protection
CS
+
-
AGND
VINDET
V
CC
0.13 V
COSC
ID
SS
ISS
+
-
0.85 VSS
1.2 V+VINDET /2
Le
Le
EN
VREF
EN
EN
ISS
250 mV
+
-
IDSS
EN
IBIAS
DMAX
COMP
RDB
VREF
IBIAS
VSD
0.200 V
EN VINDET/2
+
-
VUV
VUV
BG
+
SS Comp
VREG
-
— VISHAY.
Document Number: 69233
S-81795-Rev. C, 04-Aug-08
www.vishay.com
3
Vishay Siliconix
SiP11205
Notes:
a. Device Mounted with all leads soldered or welded to PC board.
b. Derate 25.6 mW/°C above 25 °C.
c. Derate 26.3 mW/°C above 25 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS all voltages referenced to GND = 0 V
Parameter Limit Unit
VIN, VLX
Continuous 80
V
100 ms 100
VCC 14.5
VBST
Continuous 95
100 ms 112
VBST - VLX 15
Logic Inputs - 0.3 to VCC + 0.3
Linear Inputs - 0.3 to VCC + 0.3
HV Pre-Regulator Input Current (continuous) 10 mA
Storage Temperature - 65 to 150 °C
Maximum Junction Temperature 150
Power Dissipation PowerPAK MLP44-16a, b 2564 mW
PowerPAK TSSOP-16a, c 2630
Thermal Impedance (ΘJA)PowerPAK MLP44-16a, b 39 °C/W
PowerPAK TSSOP-16a, c 38
RECOMMENDED OPERATING RANGE all voltages referenced to GND = 0 V
Parameter Limit Unit
VIN
Continuous 36 to 75
V
100 ms 100
VBST VIN + 10.5 to VIN + 13.2
VBST - VLX 10.5 to 13.2
VCC 10.5 to 13.2
Logic Inputs - 0.3 to VCC + 0.3
Linear Inputs - 0.3 to VCC + 0.3
FOSC 200 to 1000 kHz
ROSC 40 to 200 kΩ
COSC 100 to 220 pF
CSS 10 to 100 nF
CCOMP 2.2
VREF Capacitor to GND 1
µF
CBOOST 0.1
VCC Capacitor to GND 4.7
— VISHAW
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Document Number: 69233
S-81795-Rev. C, 04-Aug-08
Vishay Siliconix
SiP11205
SPECIFICATIONS
Parameter Symbol
Test Conditions
Unless Otherwise Specified
TA = - 40 °C to + 85 °C, FOSC = 800 kHz,
10.5 V VCC 13.2 V, VINDET = 4.8 V,
VIN = 48 V, RDB1 = 47.5 kΩ, RDB2 = 28.7 kΩ,
ROSC = 47.5 kΩ, COSC = 100 pF
Limits
Unit Min. Typ. Max.
Pre-Regulator
VIN Range VIN 36 48 75 V
Pre-Reg Current (cut-off) IVINLKG VIN = 75 V, VCC > 10.5 V 10 µA
Pre-Reg Current (standby) IVINSD VIN = 75 V, VINDET = 0 V 90 200
Pre-Reg Current (switching) IVIN VIN = 75 V, VINDET = 7.5 V 3.6 6.2 9 mA
Pre-Reg Output Voltage VREG VCC Voltage with VIN = 48 V 7.8 9.3 10.4 V
Pre-Reg Drive Current ISTART VCC < VREG 20 mA
Pre-Reg Load Regulation LDR ILOAD: 0 to 20 mA 100 mV
Pre-Reg Line Regulation LNR 0.05 %/V
Regulator Compensation ISRC VCC = 12 V - 35 - 20 - 10 µA
ISNK 40 87 130
VCC Supply Voltage
VCC Range VCC 10.5 12 13.2 V
Shut Down Current ISD VINDET = 0 V 50 150 350 µA
Quiescent Current IQVINDET < VREF 3.045.2
mA
Supply Current ICC VINDET > VREF 5.0 6.6 8.5
UVLO OFF-Threshold UVLOHVCC rising 7.6 9.0 10
VHysteresis HUVLO 1.2
VCC Clamp Voltage VCLAMP Force 20 mA into VCC 14 15.3 16.2
Current Sense
Current Limit Threshold 1 (MOC)aVMOC ISS = 20 µA 105 130 160 mV
Current Limit Threshold 2 (SOC)bVSOC ISS = 400 nA 165 200 235
CS to DL Delay TD150 ns
Leading Edge Blanking Period TBL DL(ON) blanking time 20
Pulse Width Modulator
Maximum Duty CyclecDMAX VIN = 42 V, VINDET = 4.2 V 47 50 %
Maximum Duty Cycle Asymmetry 1
RDB Voltage VRDB VIN = 42 V, VINDET = 4.2 V 2.06 V
Oscillator
Oscillator FrequencydFOSC 680 800 920 kHz
Oscillator Bias Voltage VROSC 2.36 V
Soft Start
Soft Start Charging Current ISS VSS = 0 - 26 - 20 - 14 µA
SS Ramp Completion Voltage VSS 4.5 V
MOC Discharge Current IDSS1 CS = VMOC 14 20 26 µA
SOC Discharge Current IDSS2 CS = VSOC 400 nA
Reset Voltage VSSL CS < VMOC 0.25 V
Reference
Output Voltage VREF VCC = 12 V 3.2 3.3 3.4 V
Short Circuit Current IREFSC VREF = 0 V - 50 - 42 mA
Load Regulation ΔVR/ΔIR0 mA ILOAD 2.5 mA - 33 - 16 mV
— VISHAY.
Document Number: 69233
S-81795-Rev. C, 04-Aug-08
www.vishay.com
5
Vishay Siliconix
SiP11205
Notes:
a. MOC stands for moderate overcurrent voltage at CS pin.
b. SOC stands for severe overcurrent voltage at CS pin.
c. The maximum duty cycle is set by the resistor ratio (RDB1/RDB2) from pin RDB to VREF at minimum VIN = 42 V.
d. Not tested. Guaranteed by driver frequency test. The driver frequency is half of the oscillator frequency.
SPECIFICATIONS
Parameter Symbol
Test Conditions
Unless Otherwise Specified
TA = - 40 °C to + 85 °C, FOSC = 800 kHz,
10.5 V VCC 13.2 V, VINDET = 4.8 V,
VIN = 48 V, RDB1 = 47.5 kΩ, RDB2 = 28.7 kΩ,
ROSC = 47.5 kΩ, COSC = 100 pF
Limits
Unit Min. Typ. Max.
VINDET Function
VINDET Pin Input Impedance RVINDET 30 46 70 kΩ
Shutdown Threshold High Voltage VSDH VINDET rising, VREF on 0.33 0.58 0.76
V
Shutdown Hysteresis Voltage HSD 0.15
Under Voltage OFF Voltage VUVH VINDET rising at ICC 3.14 3.3 3.46
Under Voltage Hysteresis Voltage HUV 0.26
Over Temperature Protection (OTP)
Activating Temperature OTPON TJ rising 160 °C
De-Activating Temperature OTPOFF TJ falling 145
High-Side MOSFET Driver (DH Output)
Output High Voltage (differential) VDHH Sourcing 10 mA, VDH - VBST - 0.3 V
Output Low Voltage (differential) VDHL Sinking 10 mA, VDH -VLX 0.3
Peak Output Sourcing Current IDHH VCC = 10.5 V, CLOAD = 3 nF - 2.2 A
Peak Output Sinking Current IDHL 1.6
Driver Frequency FDH 340 400 460 kHz
Rise Time tHR CLOAD = 3 nF 20 ns
Fall Time tHF CLOAD = 3 nF 20
Boost Pin Current (switching) IBST VLX = 75 V, VBST = VLX + VCC
1.3 2.6 3.9 mA
LX Pin Current (switching) ILX - 2.1 - 1.4 - 0.7
LX Pin Leakage Current ILX-LKG VINDET = 0 V, VLX = 40 V 10 µA
Low-Side MOSFET Driver (DL Output)
Output High Voltage (differential) VDLH Sourcing 10 mA, VDL - VCC - 0.3 V
Output Low Voltage (differential) VDLL Sinking 10 mA, VDL - VAGND 0.3
Peak Output Sourcing Current IDLH VCC = 10.5 V, CLOAD = 3 nF - 1.6 A
Peak Output Sinking Current IDLL 1.6
Driver Frequency FDL 340 400 460 kHz
Rise Time tLR CLOAD = 3 nF 20 ns
Fall Time tLF CLOAD = 3 nF 20
VISHAY. ggfiggfifig 1|| _ n _ r|| L____J
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Document Number: 69233
S-81795-Rev. C, 04-Aug-08
Vishay Siliconix
SiP11205
PACKAGE AND PIN CONFIGURATION
Notes:
For MLP44-16 package the bottom pin 1 indicator is connected to EPAD or AGND.
To p View
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
1
V
CC
COMP
CS
AGND
R
OSC
C
OSC
R
DB
V
REF
SS
PGND
DL
LX
DH
BST
V
INDET
V
IN
MLP44-16 PowerPAK PackageTSSOP-16 PowerPAK Package
TSSOP-16 MLP44-16 Symbol Description
31
VCC Pre-regulator output and supply voltage for internal circuitry
4 2 COMP Pre-regulator compensation pin
5 3 CS Current sense comparator input
6 4 AGND Analog ground (connected to package’s exposed pad)
75
VREF 3.3 V reference output and bypass capacitor connection pin
86
ROSC Oscillator resistor connection
97
COSC Oscillator capacitor connection and external frequency sync. connection
10 8 RDB Dead time setting resistor connection
11 9 SS Soft start capacitor connection
12 10 PGND Power ground
13 11 DL Primary low-side MOSFET drive signal
14 12 LX High-side MOSFET source and transformer connection node
15 13 DH Primary high-side MOSFET drive signal
16 14 BST Bootstrap voltage pin for the high-side driver
115
VINDET Shut down/under voltage/enable control pin
216
VIN High voltage pre-regulator input
ORDERING INFORMATION
Part Number Package Marking Temperature
SiP11205DQP-T1-E3 TSSOP-16 11205 - 40 °C to + 85 °C
SiP11205DLP-T1-E3 MLP44-16
— VISHAY.
Document Number: 69233
S-81795-Rev. C, 04-Aug-08
www.vishay.com
7
Vishay Siliconix
SiP11205
TIMING DIAGRAM AND SOFT START DUTY CYCLE CONTROL
HICCUP RESPONSE TO MODERATE OVERCURRENT FAULTS
Over current protection operation showing reduction in duty cycle down to the hiccup trigger point. SS continues to discharge
down to 250 mV (400 nA IDISCHARGE), and then will recharge at 20 µA.
R
DB
D
MAX.
Time
C
OSC
SS
DL
DH
SS Clamp Level
DL
DH
CS IN
CLK
Hiccup Triggered
D
MAX.
Clamp Level
Hiccup Trigger Level
SS
OC_DET
VISHAY. LJ 1.I|||l||l| 0—1
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Document Number: 69233
S-81795-Rev. C, 04-Aug-08
Vishay Siliconix
SiP11205
FEED-FORWARD FUNCTION DIAGRAM
CIRCUIT FOR FREQUENCY SYNCHRONIZATION
DETAILED OPERATIONAL DESCRIPTION
Start Up
The controller supply (VCC) is linearly regulated up to its
target voltage VREG by the on chip pre-regulator circuit.
During power up with VINDET ramping up from GND, the VCC
capacitor minimum charge current is 20 mA and the
pre-regulator voltage is typically 9.3 V. As VINDET exceeds
VREF, the DL/DH outputs are capable of driving 3 nF
MOSFET gate capacitances and hence the pre-regulator
load regulation can easily handle 120 µA to 20 mA load step
with a typical load regulation of 1 %. Startup current into the
external VCC capacitor is limited to typically 20 mA by the
internal N-Channel DMOS in the pre-regulator unless an
external power source is connected to VCC pin. This source
may be a DC supply or from external VIN by connecting a
PNP pass transistor between VIN and VCC. The VCC pin is
protected by a 20 mA clamp when this pin exceeds 14.5 V.
The clamp turns on when VCC is between 14.5 and 16 V.
When VCC exceeds the UVLO voltage (UVLOH) a soft start
cycle of the switch mode supply is initiated. The VCC supply
continues to be charged by the pre-regulator until VCC equals
VREG. During this period, between UVLOH and VREG,
excessive load may result in VCC falling below UVLOH and
stopping switch mode operation. This situation is avoided by
the hysteresis between VREG and UVLO Off-Threshold level
UVLOL.
PWM Operation
During startup, DL always turns on before DH and both
switch on and off at half the oscillator frequency. The SS
comparator compares the SS ramp with the oscillator ramp
hence the duty cycle increases as VSS increases. When SS
ramp reaches a voltage that equals to RDB voltage, the PWM
comparator, which compares RDB voltage to the oscillator
ramp, takes over and the maximum duty cycle is now set by
the oscillator ramp and RDB voltage. Refer to "Timing
diagram and soft start duty cycle control" graph for better
understanding. After soft start completion the duty cycle is
modulated by the feed-forward voltage VFF = VROSC =
VINDET/2. Since the oscillator frequency is fixed, the ramp
amplitude must increase to reduce the duty cycle set by RDB.
Mathematically, the total duty cycle is determined by the
following formula:
DTOTAL =
VRDB/(VINDET/2) = 2 x VREF x RDB1/(RDB1 + RDB2)/VINDET
V
ROSC
= V
INDET
/2 = 3.75 V
D = 90 % D = 45 %
V
RDB
= 1.89 V
2 V
BE
DL/DH
V
COSC
low line voltage
V
COSC
high line voltage
220 pF
SiP11205
COSC
100
2N3904
1 k
SYNC IN
— VISHAY. V
Document Number: 69233
S-81795-Rev. C, 04-Aug-08
www.vishay.com
9
Vishay Siliconix
SiP11205
And the duty cycle on DL or DH will then be approximately
half of DTOTAL. Please note that due to oscillator comparator
overshoot the exact duty cycle calculated using above
formula may be slightly different. To better understand the
PWM operation during start up refer to "Timing Diagram and
Soft Start Duty Cycle Control" graph, for PWM operation
after start up see "Feed-Forward Function Diagram".
For each specific application the RDB1/RDB2 ratio must be
chosen to provide maximum duty cycle with appropriate
dead time at minimum supply voltage. The voltage at RDB pin
that corresponds to maximum duty cycle at minimum input
voltage can be determined by applying a precise voltage
source on this pin for the dead time required. The SiP11205
has a stable 3.3 V reference with 3 % temperature accuracy,
so a typical 3 % duty variation and 1 % DL/DH matching can
be achieved. There will be 0.75 % duty reduction for each 1
V increase in the VIN supply range. For better system
efficiency it is recommended that the input voltage range be
limited to 42 V to 55 V.
Soft Start
The soft start circuit plays an important role in protecting the
controller. At startup it prevents high in-rush current. During
a normal start-up sequence (VCS < VMOC. VCS is the voltage
at CS pin), or following any event that would cause a
hiccup-and-soft-start sequence, CSS will be charged from
about 0 V to a final voltage of 2 VBE + VINDET/2 at a 20 µA
rate. As the voltage on the CSS rises towards the final
voltage, the maximum permitted DL and DH duty cycles will
increase from 0 % to a maximum defined by the RDB resistor
divider.
When a mild fault condition is detected (VCS = VMOC), CSS
goes into a hiccup mode until fault condition is removed. The
hiccup is activated when CSS discharges to 0.85 VSS at
20 µA and subsequently at 0.4 µA until the fault condition is
removed. Refer to "Fault Conditions and Responses" for
details.
Fault Conditions and Responses
The faults that can cause a hiccup-and-retry cycle are
moderate over-current (MOC), severe over-current (SOC),
chip level UVLO, system level UVLO, and over temperature
protection (OTP).
Prior to detailing the various fault conditions and responses,
some definitions are given:
1. A complete switching period, T, consists of two oscillator
cycles TDL and TDH.
2. TDL (TDH) is the oscillator cycle during which the DL (DH)
output is in the high state.
3. T is defined as starting at the beginning of TDL, and
terminating at the end of TDH.
Response to MOC Faults (VMOC < VCS < VSOC):
Once SiP11205 has completed a normal soft-start cycle, VSS
will be clamped at the final voltage, allowing the maximum
possible duty cycle on DL and DH.
If an MOC fault occurs following the start-up (due to a
condition such as an excessive load on the converter’s
output), SiP11205 will respond by gradually reducing the
available maximum duty cycle of its DL and DH outputs each
to be equal to approximately 42 % of their possible 47 %
maximum values. This is before any effects of deadtime
introduced by RDB are added in. This reduction in available
maximum duty cycle is achieved by reducing the voltage on
the SS pin to 4 V, as follows:
1. If VMOC < VCS < VSOC at any time during TDL, a current
of 20 µA will be drawn out of the SS pin until the
beginning of the next TDL.
2. If the voltage on the SS pin remains above the value that
would allow an available maximum DL and DH duty cycle
of 42 %, SiP11205 will continue operating.
3. If the voltage on the SS pin goes below the value that
would allow an available maximum DL and DH duty cycle
of 42 %, a hiccup interval is started, during which both DL
and DH are held in their low states.
4. The SS pin is discharged towards 0 V by a 400 nA sink
current.
5. The hiccup interval is terminated when the SS pin is
discharged to 0.25 V.
After the above actions have been taken switching on the DL
and DH outputs will then resume with a normal soft-start
cycle.
Response to MOC faults is enabled after the successful
completion of any normal soft-start cycle.
Response to SOC Faults (VCS > VSOC):
This is an immediate, single-cycle response over current
shutdown, followed by a hiccup delay and a normal soft-start
cycle. Since this is a gross fault protection mechanism, its
triggering mechanism is asynchronous to the timing of TDL
and TDH.
1. If VCS > VSOC, a hiccup interval is started, during which
both DL and DH are held in their low states.
2. The SS pin is discharged towards 0 V by a 400 nA sink
current.
3. The hiccup interval is terminated when the SS pin is
discharged to 0.25 V.
4. Switching on the DL and DH outputs will then resume
with a normal soft-start cycle.
Severe over current response is enabled at all times,
including the initial ramp-up period of the soft-start pin. This
allows SiP11205 to provide rapid fault protection for the
converter’s power train.
— VISHAW
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Document Number: 69233
S-81795-Rev. C, 04-Aug-08
Vishay Siliconix
SiP11205
Immediate Response to UVLO Faults:
The under voltage protection conditions at converter-level
(VINDET pin UVLO) and chip-level (VCC UVLO) will
immediately trigger a shutdown-and-retry SS response, with
the restart requirements being that:
1. The SS pin has been discharged at a 20 µA rate to the
0.25 V level.
2. The affected supply has recovered to its turn-on
threshold.
Once these conditions are met, switching will resume with a
normal soft-start cycle. Response to UVLO faults is enabled
at all times, including the initial ramp-up period of the soft-
start pin.
Immediate Response to an OTP Condition:
Failure of the application circuit to provide an external
voltage to the VCC pin above the VREG level may result in an
OTP condition (TJ > OTPON). Other conditions, such as
excessive ambient temperature or, where applicable, failure
of airflow over the DC-DC converter circuit, can also trigger
an OTP condition. An OTP condition will immediately trigger
a shutdown-and-retry soft start response, with the restart
requirements being that:
1. The SS pin has been discharged at a 20 µA rate to the
0.25 V level.
2. The chip junction temperature has fallen below the lower
OTP threshold.
Once these conditions are met, switching will resume with a
normal soft-start cycle. Response to the OTP condition is
enabled at all times, including the initial ramp-up period of the
soft-start pin.
Reference
The reference voltage of SiP11205 is set at 3.3 V at VREF
pin. This pin should be decoupled externally with a 0.1 µF to
1 µF capacitor to GND. Up to 5 mA may be drawn internally
from this reference to power external circuits. Note that if the
VINDET pin is pulled below 0.55 V (typical), the reference will
be turned off, and SiP11205 will enter a low-power "standby"
mode. During startup or when VREF is accidentally shorted to
ground, this pin has internal short circuit protection limiting
the source current to 50 mA. VREF load regulation for 5 mA
step is typically 0.45 %.
Oscillator
The oscillator is designed to operate from 200 kHz to 1 MHz
with temperature stability within 15 %. This operating
frequency range allows the converter to minimize the
inductor and capacitor size, improving the power density of
the converter. The oscillator frequency, and therefore the
switching frequency, is programmable by the value of
resistor and capacitor connected to the ROSC and COSC pins
respectively. Note that the switching frequency at pins DL
and DH is half of the oscillator frequency, i.e., the DL output
will be active during one oscillator cycle, and the DH during
the next oscillator cycle.
The feed-forward voltage appears at pin ROSC and equals to
VINDET/2. This voltage sets the peak voltage of the oscillator
waveform. Therefore the higher input voltage the higher
VINDET/2 and the higher oscillator peak voltage. The pulse
width of the drive signals DL and DH is then generated by
comparing the voltage at RDB pin with the oscillator output
saw tooth. The voltage at RDB pin is fixed so the higher input
voltage the narrower DL/DH pulse width and the lower the
duty cycle. (See Feed-forward Function Diagram.)
VINDET
The VINDET pin controls several modes of operation and the
modes of operation are controlled by shutdown (VSD) and
under voltage (VUV) comparators (see block diagram). When
the IC is powered solely by VIN and VINDET is less than VSDH
due to some external reset condition the pre-regulator is in
low power standby mode and the internal bias network is
powered down. When VINDET is greater than VSDH but less
than VREF and VCC is forced to 12 V the pre-regulator shuts
off drawing only leakage current from VIN and quiescent
current from VCC. In this mode the controller output drivers
remains static (non-switching). When VINDET is above VREF
the controller is enabled and both drivers are switching at half
the oscillator frequency. If SiP11205 is shut down via this pin,
its restart will be by means of a soft-start cycle, as described
under "Soft Start" and "Hiccup-Mode Operation" above.
The input impedance to ground of this pin is typically
46K ± 30 % and must be taken into account when designing
the feed-forward compensation. An external 10:1 resistor
divider ratio of supply voltage to VINDET pin is required in a
typical application.
Primary Side MOSFET Drivers
The low-side MOSFET driver is powered directly from VCC of
the chip. The high-side MOSFET however requires the gate
voltage to be higher than VIN. This is achieved with a charge
pump capacitor CBST between BST and LX, and an external
diode to charge and bootstrap the initial charge up voltage
across CBST to VCC level. On the alternate oscillator cycle
the boost diode isolates BST from VIN and hence BST and
LX steps up to VIN + VCC and VIN, respectively. This
sequencing insures that DL will always turn on before DH
during start-up. The boost capacitor value must be chosen to
meet the application droop rate requirement.
External Frequency Synchronization
The oscillator frequency of this IC can be synchronized to an
external source with a simple circuit shown in "Circuit for
Frequency Synchronization" diagram. The synchronized
frequency should not exceed 1.4 times the set frequency,
and the synchronized frequency range should not exceed
the IC frequency range.
— VISHAY. V 35 //
Document Number: 69233
S-81795-Rev. C, 04-Aug-08
www.vishay.com
11
Vishay Siliconix
SiP11205
TYPICAL CHARACTERISTICS
VREG vs. Temperature
VUV vs. Temperature
VSD vs. Temperature
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
VREG (V)
8.2
8.4
8.6
8.8
9.0
9.2
9.4
9.6
9.8
10.0
10.2
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
V
UV
(V)
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
VUVH
VUVL
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
VSD (mV)
200
300
400
500
600
700
800
VSDH
VSDL
IVIN vs. Temperature
ICC and IQ vs. Temperature
ISD vs. Temperature
Temperature (°C)
I
VIN
(mA)
- 40 - 15 10 35 60 85 110 135
4.5
5.0
5.5
6.0
6.5
7.0
7.5
V
IN
= 75 V
Temperature (°C)
ICC, IQ (mA)
- 40 - 15 10 35 60 85 110 135
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
ICC
VCC = 12 V
IQ
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
ISD (µA)
80
100
120
140
160
180
200
VISHAY. 135 135
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12
Document Number: 69233
S-81795-Rev. C, 04-Aug-08
Vishay Siliconix
SiP11205
TYPICAL CHARACTERISTICS
UVLO vs. Temperature
IDSS1 vs. Temperature
IDSS2 vs. Temperature
7.5
8.0
8.5
9.0
9.5
10
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
UVLO (V)
UVLOH
UVLOL
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
IDSS1 (µA)
15
16
17
18
19
20
21
22
23
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
IDSS2 (µA)
0.30
0.35
0.40
0.45
0.50
0.55
VSS vs. Temperature
ISS vs. Temperature
IVINSD vs. Temperature
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
V
SS
(V)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
4.8 V
7.5 V
V
INDET
= 3.6 V
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
ISS (µA)
- 22
- 21
- 20
- 19
- 18
- 17
- 16
- 15
Temperature (°C)
IVINSD (µA)
- 40 - 15 10 35 60 85 110 135
0
20
40
60
80
100
120
140
— VISHAY. V 135 135 135
Document Number: 69233
S-81795-Rev. C, 04-Aug-08
www.vishay.com
13
Vishay Siliconix
SiP11205
TYPICAL CHARACTERISTICS
DL RDSN vs. Temperature
DH RDSN vs. Temperature
FDL/FDH vs. Temperature
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
R
DSN
(Ω)
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
R
DSN
(Ω)
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
FREQ (kHz)
370
380
390
400
410
420
430
FDL
FDH
DL RDSP vs. Temperature
DH RDSP vs. Temperature
VREF vs. Temperature
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
R
DSP
(Ω)
1.5
2.0
2.5
3.0
3.5
4.0
4.5
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
RDSP (Ω)
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
Temperature (°C)
VREF (V)
3.288
3.290
3.292
3.294
3.296
3.298
3.300
3.302
3.304
- 40 - 15 10 35 60 85 110
VISHAY. V / 7 / / / / 7\\ \\25 \\ \ \
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14
Document Number: 69233
S-81795-Rev. C, 04-Aug-08
Vishay Siliconix
SiP11205
TYPICAL CHARACTERISTICS
VRDB vs. VIN
VRDB Temperature Coefficient
Duty vs. VIN
VIN (V)
1.9565
1.9570
1.9575
1.9580
1.9585
1.9590
1.9595
1.9600
1.9605
1.9610
1.9615
40 45 50 55 60
VRDB (V)
RDB2/RDB1 =
33.2 kΩ/47.5 kΩ
VRDB (V)
1.9565
1.9570
1.9575
1.9580
1.9585
1.9590
1.9595
1.9600
1.9605
1.9610
1.9615
- 40 - 15 10 35 60 85110135
Temperature (°C)
RDB2/RDB1 =
33.2 kΩ/47.5 kΩ
VIN = 40 V
30
32
34
36
38
40
42
44
46
48
50
36 41 46 51 56 61
Duty (%)
V
IN
(V)
R
DB2
/R
DB1
=
25.5 kΩ/47.5 kΩ
R
DB2
/R
DB1
=
33.2 kΩ/47.5 kΩ
VRDB vs. VIN
VRDB Temperature Coefficient
Duty vs. Temperature
2.161
2.163
2.165
2.167
40 45 50 55 60 65 70 75
VIN (V)
VRDB (V)
RDB2/RDB1 =
25.5 kΩ/47.5 kΩ
2.169
2.162
2.163
2.164
2.165
2.166
2.167
2.168
2.169
2.170
- 40 - 15 10 35 60 85110135
VRDB (V)
Temperature (°C)
RDB2/RDB1 =
25.5 kΩ/47.5 kΩ
VIN = 44 V
Duty (%)
Temperature (°C)
46.5
47.0
47.5
48.0
48.5
49.0
49.5
- 40 - 15 10 35 60 85110135
RDB2/RDB1 =
25.5 kΩ/47.5 kΩ
RDB2/RDB1 =
25.5 kΩ/47.5 kΩ
VIN = 44 V
VIN = 40 V
— VISHAY. V 135 / r” t 15
Document Number: 69233
S-81795-Rev. C, 04-Aug-08
www.vishay.com
15
Vishay Siliconix
SiP11205
TYPICAL CHARACTERISTICS
RVINDET vs. Temperature
Line and Load Regulation
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
RVINDET (kΩ)
35
40
45
50
55
60
65
8
9
10
11
12
13
14
0 3 6 9 12 15
Load Current (A)
Output Voltage (V)
V
IN
= 42 V
V
IN
= 48 V
V
IN
= 55 V
VCS vs. Temperature
Efficiency vs. Current
- 40 - 15 10 35 60 85 110 135
Temperature (°C)
VCS (mV)
100
125
150
175
200
225
VSOC
VMOC
80
84
88
92
96
03691215
Load Current (A)
Efficiency (%)
VIN = 42 V
VIN = 48 V
VIN = 55 V
YIkKun 250kS/s[ Samvle Elli No grind Npund . um cm 2:33;“ t-kfllllllzsomsls 270Auqs I V 1 Am m\ “V 27‘u‘2007 I3. .7 r-k BIII'II Smgle sin 2.50MS/s T a! M "mus mu 5 H V 271ul2007 ‘mmo cm ”tn/~95 mnthInamschAx 44nv 271mm 5 v» .n 12:32:44
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Document Number: 69233
S-81795-Rev. C, 04-Aug-08
Vishay Siliconix
SiP11205
TYPICAL WAVEFORMS
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?69233.
System Startup
Primary Drive Signal DL vs. Inductor Voltage
System Shutdown
Hiccup when Output Shorted
_ VISHAYQ AA _’_\. all“ ififififlflflh— . .i a ‘6] i WEEKEHHHE _ 7 e \ ECU] J—\ ——_—“i . A HHHflHiE . .Q. 1 .
DETAIL A CL
CL
CL
Ğ 0.07600
0.0250.075 DP
PIN 1 INDICATOR
POLISH
CL
0.7500
3
Cbbb MB
Caaa
4
8
D
6
Ne
E1 E
8
7
B
e
123
0.7500
TOP VIEW
CL
9
B
B
DETAIL A
L1
L
GAUGE PLANE
R1
R
H
SEATING PLANE
q1
0.25
EXPOSED PAD
BOTTOM VIEW
SAS
C
b
A
7
A1
A2
ccc S
SEATING PLANE
A
c
(b)
5
b1
c1
DETAIL B-B
X
Y
Package Information
Vishay Siliconix
Document Number: 72778
31-Mar-05
www.vishay.com
1 of 2
POWER IC THERMALLY ENHANCED PowerPAKR TSSOP: 14/16-LEAD
— VISHAY. ECN 57505687Rev E‘ 047Apr705 WW ADalums and to be determmed at dalum plane ADimensxons “D“ and “E1" are Io be demrmined al damm plane A
NOTES:
1. All dimensions are in millimeters (angles in degrees).
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
4. Dimension “E1” does not include internal flash or protrusion.
5. Dimension “b” does not include Dambar protrusion.
6. “N” is the maximum number of lead terminal positions for the specified package length.
7. Datums A and B to be determined at datum plane H .
8. Dimensions “D” and “E1” are to be determined at datum plane H .
9. Cross section B-B to be determined at 0.10 to 0.25 mm from the lead tip.
10. Refer to JEDEC MO-153, Issue C., Variation ABT.
11. Exposed pad will depend on the pad size of the L/F.
Package Information
Vishay Siliconix
www.vishay.com
2 of 2 Document Number: 72778
31-Mar-05
POWER IC THERMALLY ENHANCED PowerPAKR TSSOP: 14/16-LEAD
MILLIMETERS INCHES*
Dim Min Nom Max Min Nom Max
A 1.20 0.0472
A10.025 0.100 0.001 0.0039
A20.80 0.90 1.05 0.0315 0.0354 0.0413
b0.19 0.30 0.0075 0.0118
b1 0.19 0.22 0.25 0.0075 0.0087 0.0098
c0.09 0.20 0.0035 0.0079
c1 0.09 0.16 0.0035 0.0063
D4.9 5.0 5.1 0.1929 0.1968 0.2008
e0.65 BSC 0.0256 BSC
E6.2 6.4 6.6 0.2441 0.2520 0.2598
E14.3 4.4 4.5 0.1693 0.1732 0.1772
L0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.0 REF 0.0394 REF
R0.09 0.0035 − −
R1 0.09 0.0035 − −
q100 0 0
N (14) 14 14
N (16) 16 16
X2.95 3.0 3.05 0.116 0.118 0.120
Y (14) 3.15 3.2 3.25 0.124 0.126 0.128
Y (16) 2.95 3.0 3.05 0.116 0.118 0.120
aaa 0.10 0.0039
bbb 0.10 0.0039
ccc 0.05 0.0020
ddd 0.20 0.0079
ECN: S-50568—Rev. B, 04-Apr-05
DWG: 5913
*Dimensions are in mm converted to inches.
— V VISHAYQ Index Area (3/2 X 5/2)
Terminal Tip
5
Index Area
(Dń2 Eń2)
Exposed Pad 8
-B-
D
D/2
E/2
-A-
E
Caaa 2 X
Top View
AA1 A3
-C-
Seating Plane
Side View
BB
DD
AA
CC
Detail A
C0.08
Nx
9
Cccc//
D2
D2/2
Detail B
(NE-1) x e
6
N L
E2/2
E2
Detail A
2
1
N-1N
(ND-1) x e
8
Bottom View
Cbbb MA B
N b5
Datum A or B
N r
e
Terminal Tip
5
Even Terminal/Side Odd Terminal/Side
Detail B
e
e/2
4
Caaa 2 X
Package Information
Vishay Siliconix
Document Number: 72802
16-May-05
www.vishay.com
1
PowerPAKr MLP44-16 (POWER IC ONLY)
JEDEC Part Number: MO-220
W Wb — VISHAY. A1 0 0 02 0 05 0 0 0000 0 0020 A3 7 0 20 551 7 7 0 0079 7 AA 7 0 345 7 7 0 0135 7 33131 7 015 7 7 0 0059 7 55 7 0 345 7 7 0 0135 7 5 025 030 035 00095 00115 0135 5 055 7 010 7 7 0 0039 7 cc 7 015 7 7 0 0071 7 ace 7 010 7 7 0 0039 7 D A 00 550 01575 E50 132 255 27 20 01004 01063 01102 DD 7 015 7 7 0 0071 7 E A 00 550 01575 E50 52 255 1 27 20 01004 1 01063 1 01102 e 0 55 BSC 0 0255 E50 L 03 1 04 05 00115 1 00157 1 00197 N 15 1s 3, 7 ND 7 A 7 7 4 7 5 NE 7 A 7 7 4 7 e 1 51111111112 7 7 51111111112 7 7 ECN 5750794751217 E1 167May705
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters. All angels are in degrees.
3. N is the total number of terminals.
4. The terminal #1 identifier and terminal numbering convention shall conform to JESD 95-1 SPP-012. Details of terminal #1 identifier are optional, but must
be located within the zone indicated. The terminal #1 identifier may be either a molded or marked feature. The X and Y dimension will vary according to
lead counts.
5. Dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip.
6. ND and NE refer to the number of terminals on the D and E side respectively.
7. Depopulation is possible in a symmetrical fashion.
8. Variation HHD is shown for illustration only.
9. Coplanarity applies to the exposed heat sink slug as well as the terminals.
Package Information
Vishay Siliconix
www.vishay.com
2
Document Number: 72802
16-May-05
PowerPAKr MLP44-16 (Power IC Only)
JEDEC Part Number: MO-220
MILLIMETERS* INCHES
Dim Min Nom Max Min Nom Max Notes
A 0.80 0.90 1.00 0.0315 0.0354 0.0394
A1 0 0.02 0.05 0 0.0008 0.0020
A3 0.20 Ref 0.0079
AA 0.345 0.0136
aaa 0.15 0.0059
BB 0.345 0.0136
b 0.25 0.30 0.35 0.0098 0.0118 0.138 5
bbb 0.10 0.0039
CC 0.18 0.0071
ccc 0.10 0.0039
D4.00 BSC 0.1575 BSC
D2 2.55 2.7 2.8 0.1004 0.1063 0.1102
DD 0.18 0.0071
E4.00 BSC 0.1575 BSC
E2 2.55 2.7 2.8 0.1004 0.1063 0.1102
e0.65 BSC 0.0256 BSC
L 0.3 0.4 0.5 0.0118 0.0157 0.0197
N 16 16 3, 7
ND 4 46
NE 4 46
r b(min)/2 b(min)/2
* Use millimeters as the primary measurement.
ECN: S-50794—Rev. B, 16-May-05
DWG: 5905
— VISHAY. V
Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 09-Jul-2021 1Document Number: 91000
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
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