XC2Sxx0E Datasheet by Xilinx Inc.

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Product Specification
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This document includes all four modules of the Spartan®-IIE FPGA data sheet.
Module 1:
Introduction and Ordering Information
DS077-1 (v3.0) August 9, 2013
Introduction
•Features
General Overview
Product Availability
User I/O Chart
Ordering Information
Module 2:
Functional Description
DS077-2 (v3.0) August 9, 2013
Architectural Description
- Spartan-IIE Array
- Input/Output Block
- Configurable Logic Block
- Block RAM
- Clock Distribution: Delay-Locked Loop
- Boundary Scan
Development System
Configuration
Module 3:
DC and Switching Characteristics
DS077-3 (v3.0) August 9, 2013
DC Specifications
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Characteristics
- Power-On Requirements
- DC Input and Output Levels
Switching Characteristics
-Pin-to-Pin Parameters
- IOB Switching Characteristics
- Clock Distribution Characteristics
- DLL Timing Parameters
- CLB Switching Characteristics
- Block RAM Switching Characteristics
- TBUF Switching Characteristics
- JTAG Switching Characteristics
- Configuration Switching Characteristics
Module 4:
Pinout Tables
DS077-4 (v3.0) August 9, 2013
Pin Definitions
•Pinout Tables
IMPORTANT NOTE: The Spartan-IIE FPGA data sheet is in four modules. Each module has its own Revision History at the
end. Use the PDF "Bookmarks" for easy navigation in this volume.
0Spartan-IIE FPGA Family
Data Sheet
DS077 August 9, 2013 0 0 Product Specification
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Product Specification
© 2001–2013 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
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Introduction
The Spartan®-IIE Field-Programmable Gate Array family
gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
seven-member family offers densities ranging from 50,000
to 600,000 system gates, as shown in Ta bl e 1. System per-
formance is supported beyond 200 MHz.
Features include block RAM (to 288K bits), distributed RAM
(to 221,184 bits), 19 selectable I/O standards, and four
DLLs (Delay-Locked Loops). Fast, predictable interconnect
means that successive design iterations continue to meet
timing requirements.
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
Second generation ASIC replacement technology
- Densities as high as 15,552 logic cells with up to
600,000 system gates
- Streamlined features based on Virtex®-E FPGA
architecture
- Unlimited in-system reprogrammability
- Very low cost
- Cost-effective 0.15 micron technology
System level features
- SelectRAM™ hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K-bit true dual-port block RAM
· Fast interfaces to external RAM
- Fully 3.3V PCI compliant to 64 bits at 66 MHz and
CardBus compliant
- Low-power segmented routing architecture
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
· Eliminate clock distribution delay
· Multiply, divide, or phase shift
- Four primary low-skew global clock distribution nets
- IEEE 1149.1 compatible boundary scan logic
Versatile I/O and packaging
- Pb-free package options
- Low-cost packages available in all densities
- Family footprint compatibility in common packages
- 19 high-performance interface standards
· LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL
· LVDS and LVPECL differential I/O
- Up to 205 differential I/O pairs that can be input,
output, or bidirectional
- Hot swap I/O (CompactPCI friendly)
Core logic powered at 1.8V and I/Os powered at 1.5V,
2.5V, or 3.3V
Fully supported by powerful Xilinx® ISE® development
system
- Fully automatic mapping, placement, and routing
- Integrated with design entry and verification tools
- Extensive IP library including DSP functions and
soft processors
Spartan-IIE FPGA Family:
Introduction and Ordering
Information
DS077-1 (v3.0) August 9, 2013 0Product Specification
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Table 1: Spartan-IIE FPGA Family Members
Device
Logic
Cells
Typical
System Gate Range
(Logic and RAM)
CLB
Array
(R x C)
Total
CLBs
Maximum
Available
User I/O(1)
Maximum
Differential
I/O Pairs
Distributed
RAM Bits
Block RAM
Bits
XC2S50E 1,728 23,000 - 50,000 16 x 24 384 182 83 24,576 32K
XC2S100E 2,700 37,000 - 100,000 20 x 30 600 202 86 38,400 40K
XC2S150E 3,888 52,000 - 150,000 24 x 36 864 265 114 55,296 48K
XC2S200E 5,292 71,000 - 200,000 28 x 42 1,176 289 120 75,264 56K
XC2S300E 6,912 93,000 - 300,000 32 x 48 1,536 329 120 98,304 64K
XC2S400E 10,800 145,000 - 400,000 40 x 60 2,400 410 172 153,600 160K
XC2S600E 15,552 210,000 - 600,000 48 x 72 3,456 514 205 221,184 288K
Notes:
1. User I/O counts include the four global clock/user input pins. See details in Ta b l e 2, page 5
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Product Specification
Spartan-IIE FPGA Family: Introduction and Ordering Information
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General Overview
The Spartan-IIE family of FPGAs have a regular, flexible,
programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB columns. The XC2S400E has four col-
umns and the XC2S600E has six columns of block RAM.
These functional elements are interconnected by a powerful
hierarchy of versatile routing channels (see Figure 1).
Spartan-IIE FPGAs are customized by loading configura-
tion data into internal static memory cells. Unlimited repro-
gramming cycles are possible with this approach. Stored
values in these cells determine logic functions and intercon-
nections implemented in the FPGA. Configuration data can
be read from an external serial PROM (master serial mode),
or written into the FPGA in slave serial, slave parallel, or
Boundary Scan modes. Xilinx offers multiple types of
low-cost configuration solutions including the Platform
Flash in-system programmable configuration PROMs.
Spartan-IIE FPGAs are typically used in high-volume appli-
cations where the versatility of a fast programmable solution
adds benefits. Spartan-IIE FPGAs are ideal for shortening
product development cycles while offering a cost-effective
solution for high volume production.
Spartan-IIE FPGAs achieve high-performance, low-cost
operation through advanced architecture and semiconduc-
tor technology. Spartan-IIE devices provide system clock
rates beyond 200 MHz. In addition to the conventional ben-
efits of high-volume programmable logic solutions, Spar-
tan-IIE FPGAs also offer on-chip synchronous single-port
and dual-port RAM (block and distributed form), DLL clock
drivers, programmable set and reset on all flip-flops, fast
carry logic, and many other features.
Spartan-IIE Family Compared to Spartan-II
Family
Higher density and more I/O
Higher performance
Unique pinouts in cost-effective packages
Differential signaling
- LVDS, Bus LVDS, LVPECL
•V
CCINT = 1.8V
-Lower power
- 5V tolerance with external resistor
- 3V tolerance directly
PCI, LVTTL, and LVCMOS2 input buffers powered by
VCCO instead of VCCINT
Unique larger bitstream
Figure 1: Basic Spartan-IIE Family FPGA Block Diagram
DLL DLL
DLL
DLL
BLOCK RAM BLOCK RAM
BLOCK RAMBLOCK RAM
I/O LOGIC
CLBs CLBs
CLBs CLBs
DS077_01_052102
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Product Specification
Spartan-IIE FPGA Family: Introduction and Ordering Information
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Spartan-IIE Product Availability
Ta ble 2 shows the maximum user I/Os available on the device and the number of user I/Os available for each
device/package combination.
Table 2: Spartan-IIE FPGA User I/O Chart
Device
Maximum
User I/O
Available User I/O According to Package Type
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG456
FGG456
FG676
FGG676
XC2S50E 182 102 146 182 - -
XC2S100E 202 102 146 182 202 -
XC2S150E 265 -146 182 265 -
XC2S200E 289 -146 182 289 -
XC2S300E 329 -146 182 329 -
XC2S400E 410 - - 182 329 410
XC2S600E 514 ---329 514
Notes:
1. User I/O counts include the four global clock/user input pins.
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Ordering Information
Spartan-IIE devices are available in both standard and Pb-free packaging options for all device/package combinations. The
Pb-free packages include a special "G" character in the ordering code.
Standard Packaging
Pb-Free Packaging
Device Part Marking
Figure 2 is a top marking example for Spartan-IIE FPGAs in
the quad-flat packages. The markings for BGA packages
are nearly identical to those for the quad-flat packages,
except that the marking is rotated with respect to the ball A1
indicator.
The "7C" and "6I" Speed Grade/Temperature Range part
combinations may be dual marked as "7C/6I". Devices
with the dual mark can be used as either -7C or -6I devices.
Devices with a single mark are only guaranteed for the
marked speed grade and temperature range.
XC2S50E -6 PQ 208 C
Device Type
Speed Grade
Temperature Range
Package Type
Number of Pins
Example:
DS077-1_03a_072004
XC2S50E -6 PQ 208 C
Device Type
Speed Grade
Temperature Range
Package Type
Number of Pins
Pb-free
GExample:
DS077-1_03b_072004
Device Ordering Options
Device Speed Grade Package Type / Number of Pins Temperature Range ( TJ
)(2)
XC2S50E -6 Standard Performance TQ(G)144 144-pin Plastic Thin QFP C = Commercial 0°C to + 85°C
XC2S100E -7 Higher Performance(1) PQ(G)208 208-pin Plastic QFP I = Industrial 40°C to +100°C
XC2S150E FT(G)256 256-ball Fine Pitch BGA
XC2S200E FG(G)456 456-ball Fine Pitch BGA
XC2S300E FG(G)676 676-ball Fine Pitch BGA
XC2S400E
XC2S600E
Notes:
1. The -7 speed grade is exclusively available in the Commercial temperature range.
2. See www.xilinx.com for information on automotive temperature range devices.
Figure 2: Spartan-IIE QFP Marking Example
Lot Code (numeric)
Date Code
Sample package with part marking
for XC2S50E-6PQ208C.
XC2S50E
PQ208xxx0425
xxxxxxxxx
6C
SPARTAN
Device Type
Package
Speed
Operating Range
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Spartan-IIE FPGA Family: Introduction and Ordering Information
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Revision History
Date Version Description
06/27/2002 1.1 Updated -7 availability.
11/18/2002 2.0 Added XC2S400E and XC2S600E. Corrected XC2S150E max I/O count and XC2S50E
differential I/O count and updated availability.
07/09/2003 2.1 Noted hot-swap capability. Updated Table 2 to show that all products are available. Clarified
device part marking.
07/28/2004 2.2 Added information on Pb-free packaging options.
06/18/2008 2.3 Added dual mark information in Device Part Marking. Updated all modules for continuous
page, figure, and table numbering. Updated links. Synchronized all modules to v2.3.
08/09/2013 3.0 This product is obsolete/discontinued per XCN12026.
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Product Specification
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Architectural Description
Spartan-IIE FPGA Array
The Spartan®-IIE user-programmable gate array, shown in
Figure 3, is composed of five major configurable elements:
IOBs provide the interface between the package pins
and the internal logic
CLBs provide the functional elements for constructing
most logic
Dedicated block RAM memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
Versatile multi-level interconnect structure
As can be seen in Figure 3, the CLBs form the central logic
structure with easy access to all support and routing struc-
tures. The IOBs are located around all the logic and mem-
ory elements for easy and quick routing of signals on and off
the chip.
Values stored in static memory cells control all the configu-
rable logic elements and interconnect resources. These val-
ues load into the memory cells on power-up, and can reload
if necessary to change the function of the device.
Each of these elements will be discussed in detail in the fol-
lowing sections.
Spartan-IIE FPGA Family:
Functional Description
DS077-2 (v3.0) August 9, 2013 0Product Specification
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Figure 3: Basic Spartan-IIE Family FPGA Block Diagram
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Spartan-IIE FPGA Family: Functional Description
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Input/Output Block
The Spartan-IIE FPGA IOB, as seen in Figure 4, features
inputs and outputs that support a wide variety of I/O signal-
ing standards. These high-speed inputs and outputs are
capable of supporting various state of the art memory and
bus interfaces. The default standard is LVTTL. Ta b le 3 lists
several of the standards which are supported along with the
required reference (VREF), output (VCCO) and board termi-
nation (VTT) voltages needed to meet the standard. For
more details on the I/O standards and termination applica-
tion examples, see XAPP179, "Using SelectIO Interfaces in
Spartan-II and Spartan-IIE FPGAs."
The three IOB registers function either as edge-triggered
D-type flip-flops or as level-sensitive latches. Each IOB has
a clock signal (CLK) shared by the three registers and inde-
pendent Clock Enable (CE) signals for each register.
In addition to the CLK and CE control signals, the three reg-
isters share a Set/Reset (SR). For each register, this signal
can be independently configured as a synchronous Set, a
synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
A feature not shown in the block diagram, but controlled by
the software, is polarity control. The input and output buffers
and all of the IOB control signals have independent polarity
controls.
Figure 4: Spartan-IIE Input/Output Block (IOB)
Package Pin
Package
Pin
Package Pin
D
CK
EC
SR
Q
D
CK
EC
SR
Q
D
CK
EC
SR
Q
Programmable
Bias and
ESD Network
VCCO
I/O
I/O, VREF
Internal
Reference
To Next I/O
To Other
External VREF Inputs
of Bank
Notes:
1. For some I/O standards.
Programmable
Input Buffer
Programmable
Output Buffer
Programmable
Delay
VCC
VCC(1)
OE
SR
O
OCE
I
ICE
IQ
CLK
TCE
T
DS077-2_01_051501
TFF
OFF
IFF
Table 3: Standards Supported by I/O (Typical Values)
I/O Standard
Input
Reference
Voltag e
(VREF)
Input
Voltag e
(VCCO)
Output
Source
Voltag e
(VCCO)
Board
Termination
Voltag e
(VTT)
LVTTL (2-24 mA) N/A 3.3 3.3 N/A
LVCMOS2 N/A 2.5 2.5 N/A
LVCMOS18 N/A 1.8 1.8 N/A
PCI (3V,
33 MHz/66 MHz)
N/A 3.3 3.3 N/A
GTL 0.8 N/A N/A 1.2
GTL+ 1.0 N/A N/A 1.5
HSTL Class I 0.75 N/A 1.5 0.75
HSTL Class III 0.9 N/A 1.5 1.5
HSTL Class IV 0.9 N/A 1.5 1.5
SSTL3 Class I
and II
1.5 N/A 3.3 1.5
SSTL2 Class I
and II
1.25 N/A 2.5 1.25
CTT 1.5 N/A 3.3 1.5
AGP 1.32 N/A 3.3 N/A
LVDS, Bus LVDS N/A N/A 2.5 N/A
LVPE CL N/A N/A 3.3 N/A
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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Optional pull-up and pull-down resistors and an optional
weak-keeper circuit are attached to each user I/O pad. Prior
to configuration all outputs not involved in configuration are
forced into their high-impedance state. The pull-down resis-
tors and the weak-keeper circuits are inactive, but inputs
may optionally be pulled up. The activation of pull-up resis-
tors prior to configuration is controlled on a global basis by
the configuration mode pins. If the pull-up resistors are not
activated, all the pins will float. Consequently, external
pull-up or pull-down resistors must be provided on pins
required to be at a well-defined logic level prior to configura-
tion.
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. After
configuration, clamping diodes are connected to VCCO for
LVTTL, PCI, HSTL, SSTL, CTT, and AGP standards.
All Spartan-IIE FPGA IOBs support IEEE 1149.1-compati-
ble boundary scan testing.
Input Path
A buffer in the IOB input path routes the input signal directly
to internal logic and through an optional input flip-flop.
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, VREF
. The need to supply VREF imposes
constraints on which standards can used in close proximity
to each other. See I/O Banking.
There are optional pull-up and pull-down resistors at each
input for use after configuration.
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.
Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. Each output
buffer can source up to 24 mA and sink up to 48 mA. Drive
strength and slew rate controls minimize bus transients. The
default output driver is LVTTL with 12 mA drive strength and
slow slew rate.
In most signaling standards, the output high voltage
depends on an externally supplied VCCO voltage. The need
to supply VCCO imposes constraints on which standards
can be used in close proximity to each other. See I/O Bank-
ing.
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way helps eliminate bus chatter.
Because the weak-keeper circuit uses the IOB input buffer
to monitor the input level, an appropriate VREF voltage must
be provided if the signaling standard requires one. The pro-
vision of this voltage must comply with the I/O banking
rules.
I/O Banking
Some of the I/O standards described above require VCCO
and/or VREF voltages. These voltages are externally sup-
plied and connected to device pins that serve groups of
IOBs, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from separating each edge of the
FPGA into two banks (see Figure 5). The pinout tables
show the bank affiliation of each I/O (see Pinout Tables,
page 53). Each bank has multiple VCCO pins which must be
connected to the same voltage. Voltage requirements are
determined by the output standards in use.
In the TQ144 and PQ208 packages, the eight banks have
VCCO connected together. Thus, only one VCCO level is
allowed in these packages, although different VREF values
are allowed in each of the eight banks.
Within a bank, standards may be mixed only if they use the
same VCCO. Compatible standards are shown in Ta bl e 4.
GTL and GTL+ appear under all voltages because their
open-drain outputs do not depend on VCCO. Note that VCCO
Figure 5: Spartan-IIE I/O Banks
DS077-2_02_051501
Bank 0
GCLK3 GCLK2
GCLK1 GCLK0
Bank 1
Bank 5 Bank 4
Spartan-IIE
Device
Bank 7Bank 6
Bank 2Bank 3
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Spartan-IIE FPGA Family: Functional Description
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is required for most output standards and for LVTTL,
LVCMOS, and PCI inputs.
Some input standards require a user-supplied threshold
voltage, VREF
. In this case, certain user-I/O pins are auto-
matically configured as inputs for the VREF voltage. About
one in six of the I/O pins in the bank assume this role.
VREF pins within a bank are interconnected internally and
consequently only one VREF voltage can be used within
each bank. All VREF pins in the bank, however, must be con-
nected to the external voltage source for correct operation.
In a bank, inputs requiring VREF can be mixed with those
that do not but only one VREF voltage may be used within a
bank. The VCCO and VREF pins for each bank appear in the
device pinout tables.
Within a given package, the number of VREF and VCCO pins
can vary depending on the size of device. In larger devices,
more I/O pins convert to VREF pins. Since these are always
a superset of the VREF pins used for smaller devices, it is
possible to design a PCB that permits migration to a larger
device. All VREF pins for the largest device anticipated must
be connected to the VREF voltage, and not used for I/O.
See Xilinx® Application Note XAPP179 for more information
on I/O resources.
Hot Swap, Hot Insertion, Hot Socketing Support
The I/O pins support hot swap — also called hot insertion
and hot socketing — and are considered CompactPCI
Friendly according to the PCI Bus v2.2 Specification. Con-
sequently, an unpowered Spartan-IIE FPGA can be
plugged directly into a powered system or backplane with-
out affecting or damaging the system or the FPGA. The hot
swap functionality is built into every XC2S150E,
XC2S400E, and XC2S600E device. All other Spartan-IIE
devices built after Product Change Notice PCN2002-05 also
include hot swap functionality.
To support hot swap, Spartan-IIE devices include the follow-
ing I/O features.
Signals can be applied to Spartan-IIE FPGA I/O pins
before powering the FPGA’s VCCINT or VCCO supply
inputs.
Spartan-IIE FPGA I/O pins are high-impedance (i.e.,
three-stated) before and throughout the power-up and
configuration processes when employing a
configuration mode that does not enable the
preconfiguration weak pull-up resistors (see Ta b l e 11,
page 22).
There is no current path from the I/O pin back to the
VCCINT or VCCO voltage supplies.
Spartan-IIE FPGAs are immune to latch-up during hot
swap.
Once connected to the system, each pin adds a small
amount of capacitance (CIN). Likewise, each I/O consumes
a small amount of DC current, equivalent to the input leak-
age specification (IL). There also may be a small amount of
temporary AC current (IHSPO) when the pin input voltage
exceeds VCCO plus 0.4V, which lasts less than 10 ns.
A weak-keeper circuit within each user-I/O pin is enabled
during the last frame of configuration data and has no
noticeable effect on robust system signals driven by an
active driver or a strong pull-up or pull-down resistor.
Undriven or floating system signals may be affected. The
specific effect depends on how the I/O pin is configured.
User-I/O pins configured as outputs or enabled outputs
have a weak pull-up resistor to VCCO during the last config-
uration frame. User-I/O pins configured as inputs or bidirec-
tional I/Os have weak pull-down resistors. The weak-keeper
circuit turns off when the DONE pin goes High, provided
that it is not used in the configured application.
Table 4: Compatible Standards
VCCO Compatible Standards
3.3V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP,
LVPECL, GTL, GTL+
2.5V SSTL2 I, SSTL2 II, LVCMOS2, LVDS, Bus
LVDS, GTL, GTL+
1.8V LVCMOS18, GTL, GTL+
1.5V HSTL I, HSTL III, HSTL IV, GTL, GTL+
Table 5: I/O Banking
Package TQ144, PQ208
FT256, FG456,
FG676
VCCO Banks Interconnected as 1 8 independent
VREF Banks 8 independent 8 independent
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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Configurable Logic Block
The basic building block of the Spartan-IIE FPGA CLB is the
logic cell (LC). An LC includes a 4-input function generator,
carry logic, and storage element. The output from the func-
tion generator in each LC drives the CLB output or the
D input of the flip-flop. Each Spartan-IIE FPGA CLB con-
tains four LCs, organized in two similar slices; a single slice
is shown in Figure 6.
In addition to the four basic LCs, the Spartan-IIE FPGA CLB
contains logic that combines function generators to provide
functions of five or six inputs.
Look-Up Tables
Spartan-IIE FPGA function generators are implemented as
4-input look-up tables (LUTs). In addition to operating as a
function generator, each LUT can provide a 16 x 1-bit syn-
chronous RAM. Furthermore, the two LUTs within a slice
can be combined to create a 16 x 2-bit or 32 x 1-bit syn-
chronous RAM, or a 16 x 1-bit dual-port synchronous RAM.
The Spartan-IIE FPGA LUT can also provide a 16-bit shift
register that is ideal for capturing high-speed or burst-mode
data. This mode can also be used to store data in applica-
tions such as Digital Signal Processing.
Storage Elements
Storage elements in the Spartan-IIE FPGA slice can be
configured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D inputs can be driven either by
function generators within the slice or directly from slice
inputs, bypassing the function generators.
In addition to Clock and Clock Enable signals, each slice
has synchronous set and reset signals (SR and BY). SR
forces a storage element into the initialization state speci-
fied for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals may be configured to
operate asynchronously.
All control signals are independently invertible, and are
shared by the two flip-flops within the slice.
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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Additional Logic
The F5 multiplexer in each slice combines the function gen-
erator outputs (Figure 7). This combination provides either
a function generator that can implement any 5-input func-
tion, a 4:1 multiplexer, or selected functions of up to nine
inputs.
Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the two
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected func-
tions of up to 19 inputs.
Figure 6: Spartan-IIE CLB Slice (two identical slices in each CLB)
I3
I4
I2
I1
Look-Up
Table D
CK
EC
Q
R
S
I3
I4
I2
I1
O
O
Look-Up
Table D
CK
EC
Q
R
S
XQ
X
XB
CE
CLK
CIN
BX
F1
F2
F3
SR
BY
F5IN
G1
G2
YQ
Y
YB
COUT
G3
G4
F4
Carry
and
Control
Logic
Carry
and
Control
Logic
DS001_04_091400
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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Each CLB has four direct feedthrough paths, one per LC.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.
Arithmetic Logic
Dedicated carry logic provides capability for high-speed
arithmetic functions. The Spartan-IIE FPGA CLB supports
two separate carry chains, one per slice. The height of the
carry chains is two bits per CLB.
The arithmetic logic includes an XOR gate that allows a
1-bit full adder to be implemented within an LC. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementations.
The dedicated carry path can also be used to cascade func-
tion generators for implementing wide logic functions.
BUFTs
Each Spartan-IIE FPGA CLB contains two 3-state drivers
(BUFTs) that can drive on-chip busses. The IOBs on the left
and right sides can also drive the on-chip busses. See Ded-
icated Routing, page 17. Each Spartan-IIE FPGA BUFT
has an independent 3-state control pin and an independent
input pin. The 3-state control pin is an active-Low enable
(T). When all BUFTs on a net are disabled, the net is High.
There is no need to instantiate a pull-up unless desired for
simulation purposes. Simultaneously driving BUFTs onto
the same net will not cause contention. If driven both High
and Low, the net will be Low.
Block RAM
Spartan-IIE FPGAs incorporate several large block RAM
memories. These complement the distributed RAM
Look-Up Tables (LUTs) that provide shallow memory struc-
tures implemented in CLBs.
Block RAM memory blocks are organized in columns. Most
Spartan-IIE devices contain two such columns, one along
each vertical edge. The XC2S400E has four block RAM col-
umns and the XC2S600E has six block RAM columns.
These columns extend the full height of the chip. Each
memory block is four CLBs high, and consequently, a
Spartan-IIE device 16 CLBs high will contain four memory
blocks per column, and a total of eight blocks.
Each block RAM cell, as illustrated in Figure 8, is a fully syn-
chronous dual-ported 4096-bit RAM with independent con-
trol signals for each port. The data widths of the two ports
can be configured independently, providing built-in
bus-width conversion.
Figure 7: F5 and F6 Multiplexers
LUT
DS077-2_05-111501
LUT
MUXF5
MUXF6
LUT
Slice
Slice
CLB
LUT
MUXF5
Table 6: Spartan-IIE Block RAM Amounts
Spartan-IIE
Device # of Blocks
Total Block RAM
Bits
XC2S50E 832K
XC2S100E 10 40K
XC2S150E 12 48K
XC2S200E 14 56K
XC2S300E 16 64K
XC2S400E 40 160K
XC2S600E 72 288K
Figure 8: Dual-Port Block RAM
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
WEA
ENA
RSTA
CLKA
ADD[#:0]
DIA[#:0]
DOA[#:0]
DOB[#:0]
RAMB4_S#_S#
DS001_05_060100
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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Ta ble 7 shows the depth and width aspect ratios for the
block RAM.
The Spartan-IIE FPGA block RAM also includes dedicated
routing to provide an efficient interface with both CLBs and
other block RAMs. See Xilinx Application Note XAPP173 for
more information on block RAM.
Programmable Routing
It is the longest delay path that limits the speed of any
design. Consequently, the Spartan-IIE FPGA routing archi-
tecture and its place-and-route software were defined jointly
to minimize long-path delays and yield the best system per-
formance.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
The software automatically uses the best available routing
based on user timing requirements. The details are pro-
vided here for reference.
Local Routing
The local routing resources, as shown in Figure 9, provide
the following three types of connections:
Interconnections among the LUTs, flip-flops, and
General Routing Matrix (GRM), described below.
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM
General Purpose Routing
Most Spartan-IIE FPGA signals are routed on the general
purpose routing, and consequently, the majority of intercon-
nect resources are associated with this level of the routing
hierarchy. The general routing resources are located in hor-
izontal and vertical routing channels associated with the
rows and columns of CLBs. The general-purpose routing
resources are listed below.
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
96 buffered Hex lines route GRM signals to other
GRMs six blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
may be driven only at their endpoints. Hex-line signals
can be accessed either at the endpoints or at the
midpoint (three blocks from the source). One third of
the Hex lines are bidirectional, while the remaining
ones are unidirectional.
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
I/O Routing
Spartan-IIE devices have additional routing resources
around their periphery that form an interface between the
CLB array and the IOBs. This additional routing, called the
VersaRing™ routing, facilitates pin-swapping and pin-lock-
ing, such that logic redesigns can adapt to existing PCB lay-
outs. Time-to-market is reduced, since PCBs and other
system components can be manufactured while the logic
design is still in progress.
Table 7: Block RAM Port Aspect Ratios
Width Depth ADDR Bus Data Bus
14096 ADDR<11:0> DATA<0>
22048 ADDR<10:0> DATA<1:0>
41024 ADDR<9:0> DATA<3:0>
8512 ADDR<8:0> DATA<7:0>
16 256 ADDR<7:0> DATA<15:0>
Figure 9: Spartan-IIE Local Routing
DS001_06_032300
CLB
GRM
To
Adjacent
GRM
To Adjacent
GRM
Direct
Connection
To Adjacent
CLB
To Adjacent
GRM
To Adjacent
GRM
Direct Connection
To Adjacent
CLB
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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Dedicated Routing
Some classes of signal require dedicated routing resources
to maximize performance. In the Spartan-IIE FPGA archi-
tecture, dedicated routing resources are provided for two
classes of signal.
Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row, as shown in Figure 10.
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.
Global Routing
Global Routing resources distribute clocks and other sig-
nals with very high fanout throughout the device. Spar-
tan-IIE devices include two tiers of global routing resources
referred to as primary and secondary global routing
resources.
The primary global routing resources are four
dedicated global nets with dedicated input pins that are
designed to distribute high-fanout clock signals with
minimal skew. Each global clock net can drive all CLB,
IOB, and block RAM clock pins. The primary global
nets may only be driven by global buffers. There are
four global buffers, one for each global net.
The secondary global routing resources consist of 24
backbone lines, 12 across the top of the chip and 12
across the bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These secondary resources
are more flexible than the primary resources since they
are not restricted to routing only to clock pins.
Clock Distribution
The Spartan-IIE family provides high-speed, low-skew clock
distribution through the primary global routing resources
described above. A typical clock distribution net is shown in
Figure 11.
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
primary global nets that in turn drive any clock pin.
Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
selected either from these pads or from signals in the gen-
eral purpose routing.
Delay-Locked Loop (DLL)
Associated with each global clock input buffer is a fully digi-
tal Delay-Locked Loop (DLL) that can eliminate skew
between the clock input pad and internal clock-input pins
throughout the device. Each DLL can drive two global clock
networks. The DLL monitors the input clock and the distrib-
uted clock, and automatically adjusts a clock delay element
(Figure 12). Additional delay is introduced such that clock
edges reach internal flip-flops exactly one clock period after
they arrive at the input. This closed-loop system effectively
eliminates clock-distribution delay by ensuring that clock
Figure 10: BUFT Connections to Dedicated Horizontal Bus Lines
CLB CLB CLB CLB
3-State
Lines
DS001_07_090600
Figure 11: Global Clock Distribution Network
Global Clock
Spine
Global Clock
Column
GCLKPAD2
GCLKBUF2
GCLKPAD3
GCLKBUF3
GCLKBUF1
GCLKPAD1
GCLKBUF0
GCLKPAD0
Global
Clock Rows
DS001_08_060100
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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edges arrive at internal flip-flops in synchronism with clock
edges arriving at the input.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock,
can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4,
5, 8, or 16. The phase-shifted output have optional
duty-cycle correction (Figure 13).
The DLL also operates as a clock mirror. By driving the out-
put from a DLL off-chip and then back on again, the DLL can
be used to deskew a board level clock among multiple Spar-
tan-IIE devices.
In order to guarantee that the system clock is operating cor-
rectly prior to the FPGA starting up after configuration, the
DLL can delay the completion of the configuration process
until after it has achieved lock. If the DLL uses external feed-
back, apply a reset after startup to ensure consistent lock-
ing to the external signal. See Xilinx Application Note
XAPP174 for more information on DLLs.
Boundary Scan
Spartan-IIE devices support all the mandatory bound-
ary-scan instructions specified in the IEEE standard 1149.1.
A Test Access Port (TAP) and registers are provided that
implement the EXTEST, INTEST, SAMPLE/PRELOAD,
BYPASS, IDCODE, and HIGHZ instructions. The TAP also
supports two USERCODE instructions, internal scan
chains, and configuration/readback of the device.
The TAP uses dedicated package pins that always operate
using LVTTL. For TDO to operate using LVTTL, the VCCO for
Bank 2 must be 3.3V. Otherwise, TDO switches rail-to-rail
between ground and VCCO. The boundary-scan input pins
(TDI, TMS, TCK) do not have a VCCO requirement and oper-
ate with either 2.5V or 3.3V input signaling levels. TDI, TMS,
and TCK hava a default internal weak pull-up resistor, and
TDO has no default resistor. Bitstream options allow setting
any of the four TAP pins to have an internal pull-up,
pull-down, or neither.
Boundary-scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including unbonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
the bidirectional test capability after configuration facilitates
the testing of external interconnections.
Table 8 lists the boundary-scan instructions supported in
Spartan-IIE FPGAs. Internal signals can be captured during
EXTEST by connecting them to unbonded or unused IOBs.
They may also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
Figure 12: Delay-Locked Loop Block Diagram
Figure 13: DLL Output Characteristics
Clock
Distribution
Network
Variable
Delay Line
CLKOUT
Control
CLKFB
CLKIN
ds077-2_10_070203
x132_07_092599
CLKIN
CLK2X
CLK0
CLK90
CLK180
CLK270
CLKDV
CLKDV_DIVIDE=2
DUTY_CYCLE_CORRECTION=FALSE
CLK0
CLK90
CLK180
CLK270
DUTY_CYCLE_CORRECTION=TRUE
t
0 90 180 270 0 90 180 270
Table 8: Boundary-Scan Instructions
Boundary-Scan
Command
Binary
Code[4:0] Description
EXTEST 00000 Enables boundary-scan
EXTEST operation
SAMPLE/
PRELOAD
00001 Enables boundary-scan
SAMPLE/PRELOAD
operation
USER1 00010 Access user-defined
register 1
USER2 00011 Access user-defined
register 2
CFG_OUT 00100 Access the
configuration bus for
Readback
CFG_IN 00101 Access the
configuration bus for
Configuration
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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The public boundary-scan instructions are available prior to
configuration, except for USER1 and USER2. After configu-
ration, the public instructions remain available together with
any USERCODE instructions installed during the configura-
tion. While the SAMPLE/PRELOAD and BYPASS instruc-
tions are available during configuration, it is recommended
that boundary-scan operations not be performed during this
transitional period.
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.
To facilitate internal scan chains, the User Register provides
three outputs (Reset, Update, and Shift) that represent the
corresponding states in the boundary-scan internal state
machine.
Figure 14 is a diagram of the Spartan-IIE family boundary
scan logic. It includes three bits of Data Register per IOB,
the IEEE 1149.1 Test Access Port controller, and the
Instruction Register with decodes.
INTEST 00111 Enables boundary-scan
INTEST operation
USERCODE 01000 Enables shifting out
USER code
IDCODE 01001 Enables shifting out of
ID Code
HIGHZ 01010 Disables output pins
while enabling the
Bypass Register
JSTART 01100 Clock the start-up
sequence when
StartupClk is TCK
BYPASS 11111 Enables BYPASS
RESERVED All other
codes
Xilinx reserved
instructions
Table 8: Boundary-Scan Instructions (Continued)
Boundary-Scan
Command
Binary
Code[4:0] Description
Figure 14: Spartan-IIE Family Boundary Scan Logic
D Q
D Q
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
M
U
X
Bypass
Register
IOB IOB
TDO
TDI
IOB IOB IOB
1
0
1
0
1
0
1
0
1
0
sd
LE
DQ
D Q
D Q
1
0
1
0
1
0
1
0
DQ
LE
sd
sd
LE
DQ
sd
LE
DQ
IOB
D Q
1
0DQ
LE
sd
IOB.T
DATA IN
IOB.I
IOB.Q
IOB.T
IOB.I
SHIFT/
CAPTURE
CLOCK DATA
REGISTER
DATAOUT UPDATE EXTEST
DS001_09_032300
Instruction Register
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 15.
BSDL (Boundary Scan Description Language) files for
Spartan-IIE family devices are available on the Xilinx web
site.
Spartan-IIE FPGA boundary scan IDCODE values are
shown in Tabl e 9.
Development System
Spartan-IIE FPGAs are supported by the Xilinx ISE® CAE
tools. The basic methodology for Spartan-IIE FPGA design
consists of three interrelated steps: design entry, imple-
mentation, and verification. Industry-standard tools are
used for design entry and simulation, while Xilinx provides
proprietary architecture-specific tools for implementation.
The Xilinx development system is integrated under the
Xilinx Project Navigator software, providing designers with a
common user interface regardless of their choice of entry
and verification tools. The software simplifies the selection
of implementation options with pull-down menus and on-line
help.
Several advanced software features facilitate Spartan-IIE
FPGA design. CORE Generator™ tool functions, for exam-
ple, include macros with relative location constraints to
guide their placement. They help ensure optimal implemen-
tation of common functions.
For HDL design entry, the Xilinx FPGA development system
provides interfaces to several synthesis design environ-
ments.
A standard interface-file specification, Electronic Design
Interchange Format (EDIF), simplifies file transfers into and
out of the development system.
Spartan-IIE FPGAs are supported by a unified library of
standard functions. This library contains over 400 primitives
and macros, ranging from 2-input AND gates to 16-bit accu-
mulators, and includes arithmetic functions, comparators,
counters, data registers, decoders, encoders, I/O functions,
latches, Boolean functions, multiplexers, shift registers, and
barrel shifters.
The design environment supports hierarchical design entry,
with high-level designs that comprise major functional
blocks, while lower-level designs define the logic in these
blocks. These hierarchical design elements are automati-
cally combined by the implementation tools. Different
design entry tools can be combined within a hierarchical
Figure 15: Boundary Scan Bit Sequence
Bit 0 ( TDO end)
Bit 1
Bit 2
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
MODE.I
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
BSCANT.UPD
(TDI end)
DS001_10_032300
Table 9: Spartan-IIE IDCODE Values
Device
IDCODE
Version Family Array Size Manufacturer Required
XC2S50E XXXX 0000 101 0 0001 0000 0000 1001 001 1
XC2S100E XXXX 0000 101 0 0001 0100 0000 1001 001 1
XC2S150E XXXX 0000 101 0 0001 1000 0000 1001 001 1
XC2S200E XXXX 0000 101 0 0001 1100 0000 1001 001 1
XC2S300E XXXX 0000 101 0 0010 0000 0000 1001 001 1
XC2S400E XXXX 0000 101 0 0010 1000 0000 1001 001 1
XC2S600E XXXX 0000 101 0 0011 0000 0000 1001 001 1
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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design, thus allowing the most convenient entry method to
be used for each portion of the design.
Design Implementation
The place-and-route tools automatically provide the imple-
mentation flow described in this section. The partitioner
takes the EDIF netlist for the design and maps the logic into
the architectural resources of the FPGA (CLBs and IOBs,
for example). The placer then determines the best locations
for these blocks based on their interconnections and the
desired performance. Finally, the router interconnects the
blocks.
The algorithms support fully automatic implementation of
most designs. For demanding applications, however, the
user can exercise various degrees of control over the pro-
cess. User partitioning, placement, and routing information
is optionally specified during the design-entry process. The
implementation of highly structured designs can benefit
greatly from basic floorplanning.
The implementation software incorporates timing-driven
placement and routing. Designers specify timing require-
ments along entire paths during design entry. The timing
path analysis routines then recognize these user-specified
requirements and accommodate them.
Timing requirements are entered in a form directly relating
to the system requirements, such as the targeted clock fre-
quency, or the maximum allowable delay between two reg-
isters. In this way, the overall performance of the system
along entire signal paths is automatically tailored to
user-generated specifications. Specific timing information
for individual nets is unnecessary.
Design Verification
In addition to conventional software simulation, FPGA users
can use in-circuit debugging techniques. Because Xilinx
devices are infinitely reprogrammable, designs can be veri-
fied in real time without the need for extensive sets of soft-
ware simulation vectors.
The development system supports both software simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from the
design database, and back-annotates this information into
the netlist for use by the simulator. Alternatively, the user
can verify timing-critical portions of the design using the
static timing analyzer.
For in-circuit debugging, Xilinx offers a download cable,
which connects the FPGA in the target system to a PC or
workstation. After downloading the design into the FPGA,
the designer can read back the contents of the flip-flops,
and so observe the internal logic state. Simple modifica-
tions can be downloaded into the system in a matter of min-
utes.
Configuration
Configuration is the process by which the bitstream of a
design, as generated by the Xilinx development software, is
loaded into the internal configuration memory of the FPGA.
Spartan-IIE devices support both serial configuration, using
the master/slave serial and JTAG modes, as well as
byte-wide configuration employing the Slave Parallel mode.
Configuration File
Spartan-IIE devices are configured by sequentially loading
frames of data that have been concatenated into a configu-
ration file. Ta bl e 10 shows how much nonvolatile storage
space is needed for Spartan-IIE devices.
It is important to note that, while a PROM is commonly used
to store configuration data before loading them into the
FPGA, it is by no means required. Any of a number of differ-
ent kinds of under populated nonvolatile storage already
available either on or off the board (for example, hard drives,
FLASH cards, and so on) can be used.
Modes
Spartan-IIE devices support the following four configuration
modes:
Slave Serial mode
Master Serial mode
Slave Parallel mode
Boundary-scan mode
The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
the end of configuration. The selection codes are listed in
Table 11.
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected.
Table 10: Spartan-IIE Configuration File Size
Device Configuration File Size (Bits)
XC2S50E 630,048
XC2S100E 863,840
XC2S150E 1,134,496
XC2S200E 1,442,016
XC2S300E 1,875,648
XC2S400E 2,693,440
XC2S600E 3,961,632
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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Signals
There are two kinds of pins that are used to configure
Spartan-IIE devices: Dedicated pins perform only specific
configuration-related functions; the other pins can serve as
general purpose I/Os once user operation has begun.
The dedicated pins comprise the mode pins (M2, M1, M0),
the configuration clock pin (CCLK), the PROGRAM pin, the
DONE pin and the boundary-scan pins (TDI, TDO, TMS,
TCK). Depending on the selected configuration mode,
CCLK may be an output generated by the FPGA, or may be
generated externally, and provided to the FPGA as an input.
Note that some configuration pins can act as outputs. For
correct operation, these pins require a VCCO of 3.3V to drive
an LVTTL signal or 2.5V to drive an LVCMOS signal. All the
relevant pins fall in banks 2 or 3. The CS and WRITE pins
for Slave Parallel mode are located in bank 1.
For a more detailed description than that given below, see
Module 1 and XAPP176, Configuration and Readback of
the Spartan-II and Spartan-IIE FPGA Families.
The Process
The sequence of steps necessary to configure Spartan-IIE
devices are shown in Figure 16. The overall flow can be
divided into three different phases.
Initiating configuration
Configuration memory clear
Loading data frames
•Start-up
The memory clearing and start-up phases are the same for
all configuration modes; however, the steps for the loading
of data frames are different. Thus, the details for data frame
loading are described separately in the sections devoted to
each mode.
Initiating Configuration
There are two different ways to initiate the configuration pro-
cess: applying power to the device or asserting the PRO-
GRAM input.
Configuration on power-up occurs automatically unless it is
delayed by the user, as described in a separate section
below. The waveform for configuration on power-up is
shown in Configuration Switching Characteristics, page 48.
Before configuration can begin, VCCO Bank 2 must be
greater than 1.0V. Furthermore, all VCCINT power pins must
be connected to a 1.8V supply. For more information on
delaying configuration, see Clearing Configuration Memory,
page 23.
Once in user operation, the device can be re-configured
simply by pulling the PROGRAM pin Low. The device
acknowledges the beginning of the configuration process by
driving DONE Low, then enters the memory-clearing phase.
Table 11: Configuration Modes
Configuration Mode
Preconfiguration
Pull-ups M0 M1 M2
CCLK
Direction Data Width Serial DOUT
Master Serial mode No 000 Out 1Ye s
Ye s 001
Slave Parallel mode
(SelectMAP)
Ye s 010 In 8No
No 011
Boundary-Scan mode Ye s 100 N/A 1No
No 101
Slave Serial mode Ye s 110 In 1Ye s
No 111
Notes:
1. During power-on and throughout configuration, the I/O drivers will be in a high-impedance state. After configuration, all unused I/Os
(those not assigned signals) will remain in a high-impedance state. Pins used as outputs may pulse High at the end of configuration
(see Answer 10504).
2. If the Mode pins are set for preconfiguration pull-ups, those resistors go into effect once the rising edge of INIT samples the Mode
pins. They will stay in effect until GTS is released during startup, after which the UnusedPin bitstream generator option will determine
whether the unused I/Os have a pull-up, pull-down, or no resistor.
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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Clearing Configuration Memory
The device indicates that clearing the configuration memory
is in progress by driving INIT Low.
Delaying Configuration
At this time, the user can delay configuration by holding
either PROGRAM or INIT Low, which causes the device to
remain in the memory clearing phase. Note that the bidirec-
tional INIT line is driving a Low logic level during memory
clearing. Thus, to avoid contention, use an open-drain driver
to keep INIT Low.
With no delay in force, the device indicates that the memory
is completely clear by driving INIT High. The FPGA samples
its mode pins on this Low-to-High transition.
Loading Configuration Data
Once INIT is High, the user can begin loading configuration
data frames into the device. The details of loading the con-
figuration data are discussed in the sections treating the
configuration modes individually. The sequence of opera-
tions necessary to load configuration data using the serial
modes is shown in Figure 18. Loading data using the Slave
Parallel mode is shown in Figure 21, page 28.
CRC Error Checking
After the loading of configuration data, a CRC value embed-
ded in the configuration file is checked against a CRC value
calculated within the FPGA. If the CRC values do not
match, the FPGA drives INIT Low to indicate that an error
has occurred and configuration is aborted. Note that
attempting to load an incorrect bitstream causes configura-
tion to fail and can damage the device.
To reconfigure the device, the PROGRAM pin should be
asserted to reset the configuration logic. Recycling power
also resets the FPGA for configuration. See Clearing Con-
figuration Memory.
Start-up
The start-up sequence oversees the transition of the FPGA
from the configuration state to full user operation. A match
of CRC values, indicating a successful loading of the config-
uration data, initiates the sequence.
Figure 16: Configuration Flow Diagram
FPGA Drives
INIT Low
Abort Start-up
User Holding
INIT
Low?
User Holding
PROGRAM
Low?
FPGA
Drives INIT
and DONE Low
Load
Configuration
Data Frames
User Operation
Configuration
at Power-up
DS001_11_111501
No
CRC
Correct?
Yes
FPGA
Samples
Mode Pins
Delay
Configuration
Delay
Configuration
Clear
Configuration
Memory
User Pulls
PROGRAM
Low
Start-up Sequence
FPGA Drives DONE High,
Activates I/Os,
Releases GSR net
Yes
No
Yes
No
No
Yes
Configuration During
User Operation
V
CCO
AND
V
CCINT
High?
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Product Specification
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During start-up, the device performs four operations:
1. The assertion of DONE. The failure of DONE to go High
may indicate the unsuccessful loading of configuration
data.
2. The release of the Global Three State (GTS). This
activates all the I/Os to which signals are assigned. The
remaining I/Os stay in a high-impedance state with
internal weak pull-up resistors present.
3. The release of the Global Set Reset (GSR). This allows
all flip-flops to change state.
4. The assertion of Global Write Enable (GWE). This
allows all RAMs and flip-flops to change state.
By default, these operations are synchronized to CCLK.
The entire start-up sequence lasts eight cycles, called
C0-C7, after which the loaded design is fully functional. The
four operations can be selected to switch on any CCLK
cycle C1-C6 through settings in the Xilinx
Development Software. The default timing for start-up is
shown in the top half of Figure 17; heavy lines show default
settings.
The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary.
One CCLK cycle later, the Global Set/Reset (GSR) and
Global Write Enable (GWE) signals are released. This per-
mits the internal storage elements to begin changing state
in response to the logic and the user clock.
The bottom half of Figure 17 shows another commonly
used version of the start-up timing known as
Sync-to-DONE. This version makes the GTS, GSR, and
GWE events conditional upon the DONE pin going High.
This timing is important for a daisy chain of multiple FPGAs
in serial mode, since it ensures that all FPGAs go through
start-up together, after all their DONE pins have gone High.
Sync-to-DONE timing is selected by setting the GTS, GSR,
and GWE cycles to a value of DONE in the configuration
options. This causes these signals to transition one clock
cycle after DONE externally transitions High.
The sequence can also be paused at any stage until lock
has been achieved on any or all DLLs.
Serial Modes
There are two serial configuration modes. In Master Serial
mode, the FPGA controls the configuration process by driv-
ing CCLK as an output. In Slave Serial mode, the FPGA
passively receives CCLK as an input from an external agent
(e.g., a microprocessor, CPLD, or second FPGA in master
mode) that is controlling the configuration process. In both
modes, the FPGA is configured by loading one bit per CCLK
cycle. The MSB of each configuration data byte is always
written to the DIN pin first.
See Figure 18 for the sequence for loading data into the
Spartan-IIE FPGA serially. This is an expansion of the
"Load Configuration Data Frames" block in Figure 16,
page 23. Note that CS and WRITE are not normally used
during serial configuration. To ensure successful loading of
the FPGA, do not toggle WRITE with CS Low during serial
configuration.
Figure 17: Start-Up Waveforms
Start-up CLK
Default Cycles
Sync to DONE
0123 4567
01
DONE High
23 4567
Phase
Start-up CLK
Phase
DONE
GTS
GSR
GWE
DS001_13_090600
DONE
GTS
GSR
GWE
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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Slave Serial Mode
In Slave Serial mode, the FPGA’s CCLK pin is driven by an
external source, allowing the FPGA to be configured from
other logic devices such as microprocessors or in a
daisy-chain configuration. Figure 19 shows connections for
a Master Serial FPGA configuring a Slave Serial FPGA
from a PROM. A Spartan-IIE device in slave serial mode
should be connected as shown for the third device from the
left. Slave Serial mode is selected by a <11x> on the mode
pins (M0, M1, M2). The weak pull-ups on the mode pins
make slave serial the default mode if the pins are left uncon-
nected.
The serial bitstream must be setup at the DIN input pin a
short time before each rising edge of an externally gener-
ated CCLK.
Timing for Slave Serial mode is shown in Figure 24,
page 49.
Daisy Chain
Multiple FPGAs in Slave Serial mode can be daisy-chained
for configuration from a single source. After an FPGA is
configured, data for the next device is sent to the DOUT pin.
Data on the DOUT pin changes on the rising edge of CCLK.
Note that DOUT changes on the falling edge of CCLK for
some Xilinx families but mixed daisy chains are allowed.
Configuration must be delayed until INIT pins of all
daisy-chained FPGAs are High. For more information, see
Start-up, page 23.
The maximum amount of data that can be sent to the DOUT
pin for a serial daisy chain is 220-1 (1,048,575) 32-bit words,
or 33,554,400 bits, which is approximately 8 XC2S600E bit-
streams. The configuration bitstream of downstream
devices is limited to this size.
Figure 18: Loading Serial Mode Configuration Data
No
Yes
End of
Configuration
Data File?
After INIT
Goes High
User Load One
Configuration
Bit on Next
CCLK Rising Edge
To CRC Check
DS001_14_032300
Notes:
1. If the DriveDone configuration option is not active for any of the FPGAs, pull up DONE with a 330Ω resistor.
Figure 19: Master/Slave Serial Configuration Circuit Diagram
Spartan-IIE
(Master Serial)
Xilinx
PROM
PROGRAM
M2
M0 M1
DOUT
CCLK CLK
3.3V
DATA
CE CEO
RESET/OE
DIN
INIT
DONE
PROGRAM
3.3 K
DS077-2_04_061708
GND GND
VCC
3.3V
VCCO
VCCINT
1.8V3.3V 3.3V 1.8V
Spartan-IIE
(Slave)
DONE INIT
PROGRAM
CCLK
DIN DOUT
M2
M0 M1
GND
VCCO
VCCINT
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Product Specification
Spartan-IIE FPGA Family: Functional Description
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Master Serial Mode
In Master Serial mode, the CCLK output of the FPGA drives
a Xilinx PROM, which feeds a serial stream of configuration
data to the FPGAs DIN input. Figure 19 shows a Master
Serial FPGA configuring a Slave Serial FPGA from a
PROM. A Spartan-IIE device in Master Serial mode should
be connected as shown for the device on the left side. Mas-
ter Serial mode is selected by a <00x> on the mode pins
(M0, M1, M2). The PROM RESET pin is driven by INIT, and
the CE input is driven by DONE. For more information on
serial PROMs, see the Xilinx Configuration PROM data
sheets at www.xilinx.com.
The interface is identical to the slave serial mode except
that an oscillator internal to the FPGA is used to generate
the configuration clock (CCLK). Any of a number of different
frequencies ranging from 4 to 60 MHz can be set using the
ConfigRate option in the Xilinx development software.
When selecting a CCLK frequency, ensure that the serial
PROM and any daisy-chained FPGAs are fast enough to
support the clock rate. On power-up, while the first 60 bytes
of the configuration data are being loaded, the CCLK fre-
quency is always 2.5 MHz. This frequency is used until the
ConfigRate bits, part of the configuration file, have been
loaded into the FPGA, at which point the frequency
changes to the selected ConfigRate. Unless a different fre-
quency is specified in the design, the default ConfigRate is
4 MHz. The frequency of the CCLK signal created by the
internal oscillator has a variance of +45%, –30% from the
specified value.
The FPGA accepts one bit of configuration data on each ris-
ing CCLK edge. After the FPGA has been loaded, the data
for the next device in a daisy-chain is presented on the
DOUT pin after the rising CCLK edge. The timing for Master
Serial mode is shown in Figure 25, page 49.
Slave Parallel Mode (SelectMAP)
The Slave Parallel mode, also known as SelectMAP, is the
fastest configuration option. Byte-wide data is written into
the FPGA on the D0-D7 pins. Note that D0 is the MSB of
each byte for configuration. A BUSY flag is provided for con-
trolling the flow of data at a clock frequency above 50 MHz.
Figure 20, page 27 shows the connections for two
Spartan-IIE devices using the Slave Parallel mode. Slave
Parallel mode is selected by a <011> on the mode pins (M0,
M1, M2).
The agent controlling configuration is not shown. Typically, a
processor, a microcontroller, or CPLD controls the Slave
Parallel interface. The controlling agent provides byte-wide
configuration data, CCLK, a Chip Select (CS) signal and a
Write signal (WRITE). If BUSY is asserted (High) by the
FPGA, the data must be held until BUSY goes Low.
After configuration, the pins of the Slave Parallel port
(D0-D7) can be used as additional user I/O. Alternatively,
the port may be retained to permit high-speed 8-bit read-
back. Then data can be read by deasserting WRITE. If
retention is selected, prohibit the D0-D7 pins from being
used as user I/O. See Readback, page 28.
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Product Specification
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Multiple Spartan-IIE FPGAs can be configured using the
Slave Parallel mode, and be made to start-up simultane-
ously. To configure multiple devices in this way, wire the indi-
vidual CCLK, Data, WRITE, and BUSY pins of all the
devices in parallel. The individual devices are loaded sepa-
rately by asserting the CS pin of each device in turn and
writing the appropriate data. Sync-to-DONE start-up timing
is used to ensure that the start-up sequence does not begin
until all the FPGAs have been loaded. See Start-up,
page 23.
Write
When using the Slave Parallel Mode, write operations send
packets of byte-wide configuration data into the FPGA.
Figure 21, page 28 shows a flowchart of the write sequence
used to load data into the Spartan-IIE FPGA. This is an
expansion of the "Load Configuration Data Frames" block in
Figure 16, page 23.
The timing for Slave Parallel mode is shown in Figure 26,
page 50.
For the present example, the user holds WRITE and CS
Low throughout the sequence of write operations. Note that
when CS is asserted on successive CCLKs, WRITE must
remain either asserted or deasserted. Otherwise an abort
will be initiated, as in the next section.
1. Drive data onto D0-D7. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more than one device’s CS should be asserted.
2. On the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this happens.
3. Repeat steps 1 and 2 until all the data has been sent.
4. Deassert CS and WRITE.
Figure 20: Slave Parallel Configuration Circuit Diagram
M1 M2
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE INIT
CCLK
DATA[7:0]
WRITE
BUSY
CS(0)
Spartan-IIE
DONE
INIT
PROGRAM
M1 M2
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE INIT
CS(1)
Spartan-IIE
DS077-2_06_110102
GND GND
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If CCLK is slower than FCCNH, the FPGA will never assert
BUSY. In this case, the above handshake is unnecessary,
and data can simply be entered into the FPGA every CCLK
cycle.
A configuration packet does not have to be written in one
continuous stretch, rather it can be split into many write
sequences. Each sequence would involve assertion of CS.
In applications where multiple clock cycles may be required
to access the configuration data before each byte can be
loaded into the Slave Parallel interface, a new byte of data
may not be ready for each consecutive CCLK edge. In such
a case the CS signal may be deasserted until the next byte
is valid on D0-D7. While CS is High, the Slave Parallel inter-
face does not expect any data and ignores all CCLK transi-
tions. However, to avoid aborting configuration, WRITE
must continue to be asserted while CS is asserted during
CCLK transitions.
Abort
To abort configuration during a write sequence, deassert
WRITE while holding CS Low. The abort operation is initi-
ated at the rising edge of CCLK. The device will remain
BUSY until the aborted operation is complete. After aborting
configuration, data is assumed to be unaligned to word
boundaries and the FPGA requires a new synchronization
word prior to accepting any new packets.
Boundary-Scan Configuration Mode
In the boundary-scan mode, no nondedicated pins are
required, configuration being done entirely through the
IEEE 1149.1 Test Access Port (TAP).
Configuration through the TAP uses the special CFG_IN
instruction. This instruction allows data input on TDI to be
converted into data packets for the internal configuration
bus.
The following steps are required to configure the FPGA
through the boundary-scan port.
1. Load the CFG_IN instruction into the boundary-scan
instruction register (IR)
2. Enter the Shift-DR (SDR) state
3. Shift a standard configuration bitstream into TDI
4. Return to Run-Test-Idle (RTI)
5. Load the JSTART instruction into IR
6. Enter the SDR state
7. Clock TCK (if selected) through the startup sequence
(the length is programmable)
8. Return to RTI
Configuration and readback via the TAP is always available.
The boundary-scan mode simply locks out the other modes.
The boundary-scan mode is selected by a <10x> on the
mode pins (M0, M1, M2). Note that the PROGRAM pin must
be pulled High prior to reconfiguration. A Low on the PRO-
GRAM pin resets the TAP controller and no boundary scan
operations can be performed. See Xilinx Application Note
XAPP188 for more information on boundary-scan configu-
ration.
Readback
The configuration data stored in the Spartan-IIE FPGA con-
figuration memory can be read back for verification. Along
with the configuration data it is possible to read back the
contents of all flip-flops/latches, LUT RAMs, and block
RAMs. This capability is used for real-time debugging.
For more detailed information see Xilinx Application Note
XAPP176, Configuration and Readback of the Spartan-II
and Spartan-IIE FPGA Families.
Figure 21: Loading Configuration Data for the Slave
Parallel Mode
Yes
No
FPGA
Driving BUSY
High?
After INIT
Goes High
Load One
Configuration
Byte on Next
CCLK Rising Edge
To CRC Check
DS001_19_032300
No
End of
Configuration
Data File?
Yes
User Drives
WRITE and CS
Low
User Drives
WRITE and CS
High
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Product Specification
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Revision History
Date Version Description
11/15/2001 1.0 Initial Xilinx release.
11/18/2002 2.0 Added XC2S400E and XC2S600E. Removed Preliminary designation. Clarified details of I/O
standards, boundary scan, and configuration.
07/09/2003 2.1 Added hot swap description (see Hot Swap, Hot Insertion, Hot Socketing Support). Added
Table 9 containing JTAG IDCODE values. Clarified configuration PROM support.
06/18/2008 2.3 Added note that TDI, TMS, and TCK have a default pull-up resistor. Add note on maximum
daisy-chain limit. Updated Figure 19 since Mode pins can be pulled up to either 2.5V or 3.3V.
Updated all modules for continuous page, figure, and table numbering. Updated links.
Synchronized all modules to v2.3.
08/09/2013 3.0 This product is obsolete/discontinued per XCN12026.
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Product Specification
© 2001–2013 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Definition of Terms
In this document, some specifications may be designated as Advance or Preliminary. These designations are based on the
more detailed timing information used by the development system and reported in the output files. These terms are defined
as follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values
are subject to change. Use as estimates, not for production.
Preliminary: Based on characterization. Further changes are not expected.
Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions. The parameters included are common to popular designs and typical applications. All specifications
are subject to change without notice.
DC Specifications
Absolute Maximum Ratings
(1)
Spartan-IIE FPGA Family:
DC and Switching Characteristics
DS077-3 (v3.0) August 9, 2013 0Product Specification
Symbol Description Min Max Units
VCCINT Supply voltage relative to GND –0.5 2.0 V
VCCO Supply voltage relative to GND –0.5 4.0 V
VREF Input reference voltage –0.5 4.0 V
VIN Input voltage relative to GND
(2,3) –0.5 4.0 V
VTS Voltage applied to 3-state output(3) –0.5 4.0 V
TSTG Storage temperature (ambient) –65 +150 °C
TJJunction temperature -+125 °C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. VIN should not exceed VCCO by more than 3.6V over extended periods of time (e.g., longer than a day).
3. Maximum DC overshoot must be limited to either VCCO + 0.5V or 10 mA, and undershoot must be limited to –0.5V or 10 mA,
whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot to –2.0V or overshoot
to VCCO + 2.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA.
4. For soldering guidelines, see the Packaging Information on the Xilinx® website.
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Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
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Recommended Operating Conditions
DC Characteristics Over Operating Conditions
Symbol Description Min Max Units
TJ Junction temperature Commercial 085 °C
Industrial –40 100 °C
VCCINT Supply voltage relative to GND
(1) Commercial 1.8 – 5% 1.8 + 5% V
Industrial 1.8 – 5% 1.8 + 5% V
VCCO Supply voltage relative to GND
(2) Commercial 1.2 3.6 V
Industrial 1.2 3.6 V
TIN Input signal transition time
(3) -250 ns
Notes:
1. Functional operation is guaranteed down to a minimum VCCINT of 1.62V (Nominal VCCINT –10%). For every 50 mV reduction in
VCCINT below 1.71V (nominal VCCINT –5%), all delay parameters increase by approximately 3%.
2. Minimum and maximum values for VCCO vary according to the I/O standard selected.
3. Input and output measurement threshold is ~50% of VCCO. See Delay Measurement Methodology, page 41 for specific details.
Symbol Description Min Typ Max Units
VDRINT Data retention VCCINT voltage (below which configuration data may
be lost)
1.5 - - V
VDRIO Data retention VCCO voltage (below which configuration data may be
lost)
1.2 - - V
ICCINTQ Quiescent VCCINT supply current
(1) XC2S50E Commercial -10 200 mA
Industrial -10 200 mA
XC2S100E Commercial -10 200 mA
Industrial -10 200 mA
XC2S150E Commercial -10 300 mA
Industrial -10 300 mA
XC2S200E Commercial -10 300 mA
Industrial -10 300 mA
XC2S300E Commercial -12 300 mA
Industrial -12 300 mA
XC2S400E Commercial -15 300 mA
Industrial -15 300 mA
XC2S600E Commercial -15 400 mA
Industrial -15 400 mA
ICCOQ Quiescent VCCO supply current
(1) - - 2 mA
IREF VREF current per VREF pin - - 20 μA
ILInput or output leakage current per pin –10 -+10 μA
CIN Input capacitance (sample tested) TQ, PQ, FG, FT packages - - 8 pF
IRPU Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V
(sample tested)
(2)
- - 0.25 mA
IRPD Pad pull-down (when selected) @ VIN = 3.6V (sample tested)
(2) - - 0.25 mA
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not provide valid logic levels when input pins are connected to other circuits.
Xxmw (seer hllp://www.xi|inx.com/support/documeniaiion/customerinotices/panOOZ-OS. pdf oie XAFF450 "Power-On Current Requirements forihe Spartan-ll and Spartan-HE Families" www.xilinx.com
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Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
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Power-On Requirements
Spartan®-IIE FPGAs require that a minimum supply current
ICCPO be provided to the VCCINT lines for a successful
power-on. If more current is available, the FPGA can con-
sume more than ICCPO min., though this cannot adversely
affect reliability.
A maximum limit for ICCPO is not specified. Be careful when
using foldback/crowbar supplies and fuses. It is possible to
control the magnitude of ICCPO by limiting the supply current
available to the FPGA. A current limit below the trip level will
avoid inadvertently activating over-current protection cir-
cuits.
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for VOL and VOH are guaranteed output voltages
over the recommended operating conditions. Only selected
standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards
are tested at minimum VCCO with the respective IOL and IOH
currents shown. Other standards are sample tested.
Symbol Description Min(1) Typ Max Units
I
CCPO Total V CCINT supply current
required during power-on
Commercial XC2S50E - XC2S300E After PCN(2) 300 - - mA
Before
PCN(2)
500 - - mA
XC2S400E - XC2S600E 500 - - mA
Industrial XC2S50E - XC2S300E After PCN(2) 500 - - mA
Before
PCN(2)
2 - - A
XC2S400E - XC2S600E 700 - - mA
TCCPO VCCINT(3,4) ramp time After PCN(2) 500 - - μs
Before PCN(2) 2 - 50 ms
IHSPO AC current per pin during power-on in
hot-swap applications when
VIN > VCCO + 0.4V; duration < 10ns
After PCN(2) -±60 -μA
Notes:
1. The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCCINT ramps from 0 to 1.8V.
2. Devices built after the Product Change Notice PCN 2002-05 (see
http://www.xilinx.com/support/documentation/customer_notices/pcn2002-05.pdf) have improved power-on requirements. Devices
after the PCN have a ‘T’ preceding the date code as referenced in the PCN. Note that the XC2S150E, XC2S400E, and XC2S600E
always have this mark. Devices before the PCN have an ‘S’ preceding the date code. Note that devices before the PCN are
measured with VCCINT and VCCO powering up simultaneously.
3. The ramp time is measured from GND to 1.8V on a fully loaded board.
4. VCCINT must not dip in the negative direction during power on.
5. I/Os are not guaranteed to be disabled until VCCINT is applied.
6. For more information on designing to meet the power-on specifications, refer to the application note XAPP450 "Power-On Current
Requirements for the Spartan-II and Spartan-IIE Families".
Input/Output
Standard
VIL VIH VOL VOH IOL IOH
V, M i n V, Max V, M i n V, M ax V, M a x V, M i n mA mA
LVTTL(1) –0.5 0.8 2.0 3.6 0.4 2.4 24 –24
LVCMOS2 –0.5 0.7 1.7 2.7 0.4 1.9 12 –12
LVCMOS18 –0.5 35% VCCO 65% VCCO 1.95 0.4 VCCO – 0.4 8–8
PCI, 3.3V –0.5 30% VCCO 50% VCCO VCCO + 0.5 10% VCCO 90% VCCO Note (2) Note (2)
GTL –0.5 VREF – 0.05 VREF + 0.05 3.6 0.4 -40 -
GTL+ –0.5 VREF – 0.1 VREF + 0.1 3.6 0.6 -36 -
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Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
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LVDS DC Specifications
LVPECL DC Specifications
These values are valid at the output of the source termina-
tion pack shown under LVPECL, with a 100Ω differential
load only. The VOH levels are 200 mV below standard
LVPECL levels and are compatible with devices tolerant of
lower common-mode ranges. The following table summa-
rizes the DC output specifications of LVPECL.
HSTL I –0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 8–8
HSTL III –0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 24 –8
HSTL IV –0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 48 –8
SSTL3 I –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.6 VREF + 0.6 8–8
SSTL3 II –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.8 VREF + 0.8 16 –16
SSTL2 I –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.61 VREF + 0.61 7.6 –7.6
SSTL2 II –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.8 VREF + 0.8 15.2 –15.2
CTT –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.4 VREF + 0.4 8–8
AGP –0.5 VREF – 0.2 VREF + 0.2 3.6 10% VCCO 90% VCCO Note (2) Note (2)
Notes:
1. VOL and VOH for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
Symbol Description Conditions Min Typ Max Units
VCCO Supply voltage 2.375 2.5 2.625 V
VOH Output High voltage for Q and Q RT = 100Ω across Q and Q signals 1.25 1.425 1.6 V
VOL Output Low voltage for Q and Q RT = 100Ω across Q and Q signals 0.9 1.075 1.25 V
VODIFF Differential output voltage (Q – Q),
Q = High or (Q – Q), Q = High
RT = 100Ω across Q and Q signals 250 350 450 mV
VOCM Output common-mode voltage RT = 100Ω across Q and Q signals 1.125 1.25 1.375 V
VIDIFF Differential input voltage (Q – Q),
Q = High or (Q – Q), Q = High
Common-mode input voltage = 1.25 V 100 350 -mV
VICM Input common-mode voltage Differential input voltage = ±350 mV 0.2 1.25 2.2 V
Input/Output
Standard
VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
DC Parameter Min Max Min Max Min Max Units
VCCO 3.0 3.3 3.6 V
VOH 1.8 2.11 1.92 2.28 2.13 2.41 V
VOL 0.96 1.27 1.06 1.43 1.30 1.57 V
VIH 1.49 2.72 1.49 2.72 1.49 2.72 V
VIL 0.86 2.125 0.86 2.125 0.86 2.125 V
Differential input voltage 0.3 -0.3 -0.3 - V
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Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
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Switching Characteristics
Internal timing parameters are derived from measuring
internal test patterns. Listed below are representative val-
ues. For more specific, more precise, and worst-case guar-
anteed data, use the values reported by the static timing
analyzer (TRACE in the Xilinx Development System) and
back-annotated to the simulation netlist. All timing parame-
ters assume worst-case operating conditions (supply volt-
age and junction temperature). Values apply to all
Spartan-IIE devices unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)(1)
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)(1)
Symbol Description
Speed Grade
Units
All -7 -6
Min Max Max
TICKOFDLL LVTTL global clock input to output delay using
output flip-flop for LVTTL, 12 mA, fast slew rate,
with DLL.
1.0 3.1 3.1 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology,
page 41.
3. DLL output jitter is already included in the timing calculation.
4. For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different
Standards(1), page 40. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
Symbol Description Device
Speed Grade
Units
All -7 -6
Min Max Max
TICKOF LVTTL global clock input to output
delay using output flip-flop for
LVTTL, 12 mA, fast slew rate,
without DLL.
XC2S50E 1.5 4.4 4.6 ns
XC2S100E 1.5 4.4 4.6 ns
XC2S150E 1.5 4.5 4.7 ns
XC2S200E 1.5 4.5 4.7 ns
XC2S300E 1.5 4.5 4.7 ns
XC2S400E 1.5 4.6 4.8 ns
XC2S600E 1.6 4.7 4.9 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology,
page 41.
3. For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different
Standards(1), page 40. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
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Product Specification
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Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)
Symbol Description
Speed Grade
Units
-7 -6
Min Min
TPSDLL / TPHDLL Input setup and hold time relative to global clock input signal
for LVTTL standard, no delay, IFF,(1) with DLL
1.6 / 0 1.7 / 0 ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. DLL output jitter is already included in the timing calculation.
4. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different
Standards, page 38. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
5. A zero hold time listing indicates no hold time or a negative hold time.
Symbol Description Device
Speed Grade
Units
-7 -6
Min Min
TPSFD / TPHFD Input setup and hold time relative
to global clock input signal for
LVTTL standard, with delay, IFF,(1)
without DLL
XC2S50E 1.8 / 0 1.8 / 0 ns
XC2S100E 1.8 / 0 1.8 / 0 ns
XC2S150E 1.9 / 0 1.9 / 0 ns
XC2S200E 1.9 / 0 1.9 / 0 ns
XC2S300E 2.0 / 0 2.0 / 0 ns
XC2S400E 2.0 / 0 2.0 / 0 ns
XC2S600E 2.1 / 0 2.1 / 0 ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different
Standards, page 38. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
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Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
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IOB Input Switching Characteristics
(1)
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in IOB Input Delay Adjustments for Different Standards, page 38.
Symbol Description Device
Speed Grade
Units
-7 -6
Min Max Min Max
Propagation Delays
TIOPI Pad to I output, no delay All 0.4 0.8 0.4 0.8 ns
TIOPID Pad to I output, with delay All 0.5 1.0 0.5 1.0 ns
TIOPLI Pad to output IQ via transparent latch,
no delay
All 0.7 1.5 0.7 1.6 ns
TIOPLID Pad to output IQ via transparent latch,
with delay
XC2S50E 1.3 3.0 1.3 3.1 ns
XC2S100E 1.3 3.0 1.3 3.1 ns
XC2S150E 1.3 3.2 1.3 3.3 ns
XC2S200E 1.3 3.2 1.3 3.3 ns
XC2S300E 1.3 3.2 1.3 3.3 ns
XC2S400E 1.4 3.2 1.4 3.4 ns
XC2S600E 1.5 3.5 1.5 3.7 ns
Sequential Delays
TIOCKIQ Clock CLK to output IQ All 0.1 0.7 0.1 0.7 ns
Setup/Hold Times with Respect to Clock CLK
TIOPICK / TIOICKP Pad, no delay All 1.4 / 0 -1.5 / 0 -ns
TIOPICKD / TIOICKPD Pad, with delay XC2S50E 2.9 / 0 -2.9 / 0 -ns
XC2S100E 2.9 / 0 -2.9 / 0 -ns
XC2S150E 3.1 / 0 -3.1 / 0 -ns
XC2S200E 3.1 / 0 -3.1 / 0 -ns
XC2S300E 3.1 / 0 -3.1 / 0 -ns
XC2S400E 3.2 / 0 -3.2 / 0 -ns
XC2S600E 3.5 / 0 -3.5 / 0 -ns
TIOICECK / TIOCKICE ICE input All 0.7 / 0.01 -0.7 / 0.01 -ns
Set/Reset Delays
TIOSRCKI SR input (IFF, synchronous) All 0.9 -1.0 -ns
TIOSRIQ SR input to IQ (asynchronous) All 0.5 1.2 0.5 1.4 ns
TGSRQ GSR to output IQ All 3.8 8.5 3.8 9.7 ns
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 41.
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Product Specification
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IOB Input Delay Adjustments for Different Standards
Input delays associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values shown. A
delay adjusted in this way constitutes a worst-case limit.
Symbol Description Standard
Speed Grade
Units-7 -6
Data Input Delay Adjustments
TILVTTL Standard-specific data input delay
adjustments
LVTTL 0 0 ns
TILVCMOS2 LV CMOS2 0 0 ns
TILVCMOS18 LVCMOS 1 8 0.20 0.20 ns
TILVDS LVDS 0.15 0.15 ns
TILVPECL LVPECL 0.15 0.15 ns
TIPCI33_3 PCI, 33 MHz, 3.3V 0.08 0.08 ns
TIPCI66_3 PCI, 66 MHz, 3.3V –0.11 –0.11 ns
TIGTL GTL 0.14 0.14 ns
TIGTLP GTL+ 0.14 0.14 ns
TIHSTL HSTL 0.04 0.04 ns
TISSTL2 SSTL2 0.04 0.04 ns
TISSTL3 SSTL3 0.04 0.04 ns
TICTT CTT 0.10 0.10 ns
TIAGP AGP 0.04 0.04 ns
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Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
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IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in IOB Output Delay Adjustments for Different Standards(1), page 40.
Symbol Description
Speed Grade
Units
-7 -6
Min Max Min Max
Propagation Delays
TIOOP O input to pad 1.0 2.7 1.0 2.9 ns
TIOOLP O input to pad via transparent latch 1.2 3.1 1.2 3.4 ns
3-state Delays
TIOTHZ T input to pad high impedance
(1) 0.7 1.7 0.7 1.9 ns
TIOTON T input to valid data on pad 1.1 2.9 1.1 3.1 ns
TIOTLPHZ T input to pad high impedance via transparent latch
(1) 0.8 2.0 0.8 2.2 ns
TIOTLPON T input to valid data on pad via transparent latch 1.2 3.2 1.2 3.4 ns
TGTS GTS to pad high impedance
(1) 1.9 4.6 1.9 4.9 ns
Sequential Delays
TIOCKP Clock CLK to pad 0.9 2.8 0.9 2.9 ns
TIOCKHZ Clock CLK to pad high impedance (synchronous)(1) 0.7 2.0 0.7 2.2 ns
TIOCKON Clock CLK to valid data on pad (synchronous) 1.1 3.2 1.1 3.4 ns
Setup/Hold Times with Respect to Clock CLK
TIOOCK / TIOCKO O input 1.0 / 0 -1.1 / 0 -ns
TIOOCECK / TIOCKOCE OCE input 0.7 / 0 -0.7 / 0 -ns
TIOSRCKO / TIOCKOSR SR input (OFF) 0.9 / 0 -1.0 / 0 -ns
TIOTCK / TIOCKT 3-state setup times, T input 0.6 / 0 -0.7 / 0 -ns
TIOTCECK / TIOCKTCE 3-state setup times, TCE input 0.6 / 0 -0.8 / 0 -ns
TIOSRCKT / TIOCKTSR 3-state setup times, SR input (TFF) 0.9 / 0 -1.0 / 0 -ns
Set/Reset Delays
TIOSRP SR input to pad (asynchronous) 1.2 3.3 1.2 3.5 ns
TIOSRHZ SR input to pad high impedance (asynchronous)(1) 1.0 2.4 1.0 2.7 ns
TIOSRON SR input to valid data on pad (asynchronous) 1.4 3.7 1.4 3.9 ns
TIOGSRQ GSR to pad 3.8 8.5 3.8 9.7 ns
Notes:
1. Three-state turn-off delays should not be adjusted.
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Product Specification
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IOB Output Delay Adjustments for Different Standards(1)
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit.
Symbol Description Standard
Speed Grade
Units-7 -6
Output Delay Adjustments (Adj)
TOLVTTL_S2 Standard-specific adjustments for
output delays terminating at pads
(based on standard capacitive
load, CSL)
LVTTL, Slow, 2 mA 14.7 14.7 ns
TOLVTTL_S4 4 mA 7.5 7.5 ns
TOLVTTL_S6 6 mA 4.8 4.8 ns
TOLVTTL_S8 8 mA 3.0 3.0 ns
TOLVTTL_S12 12 mA 1.9 1.9 ns
TOLVTTL_S16 16 mA 1.7 1.7 ns
TOLVTTL_S24 24 mA 1.3 1.3 ns
TOLVTTL_F2 LVTTL, Fast, 2 mA 13.1 13.1 ns
TOLVTTL_F4 4 mA 5.3 5.3 ns
TOLVTTL_F6 6 mA 3.1 3.1 ns
TOLVTTL_F8 8 mA 1.0 1.0 ns
TOLVTTL_F12 12 mA 0 0 ns
TOLVTTL_F16 16 mA –0.05 –0.05 ns
TOLVTTL_F24 24 mA –0.20 –0.20 ns
TOLVCMOS2 LVC M OS2 0.09 0.09 ns
TOLVCMOS18 LVCM OS18 0.7 0.7 ns
TOLVDS LVDS –1.2 –1.2 ns
TOLVPECL LVPECL –0.41 –0.41 ns
TOPCI33_3 PCI, 33 MHz, 3.3V 2.3 2.3 ns
TOPCI66_3 PCI, 66 MHz, 3.3V –0.41 –0.41 ns
TOGTL GTL 0.49 0.49 ns
TOGTLP GTL+ 0.8 0.8 ns
TOHSTL_I HSTL I –0.51 –0.51 ns
TOHSTL_III HSTL III –0.91 –0.91 ns
TOHSTL_IV HSTL IV –1.01 –1.01 ns
TOSSTL2_I SSTL2 I –0.51 –0.51 ns
TOSSLT2_II SSTL2 II –0.91 –0.91 ns
TOSSTL3_I SSTL3 I –0.51 –0.51 ns
TOSSTL3_II SSTL3 II –1.01 –1.01 ns
TOCTT CTT –0.61 –0.61 ns
TOAGP AGP –0.91 –0.91 ns
Notes:
1. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see the
tables Constants for Calculating TIOOP and Delay Measurement Methodology, page 41.
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Calculation of TIOOP as a Function of
Capacitance
TIOOP is the propagation delay from the O Input of the IOB
to the pad. The values for TIOOP are based on the standard
capacitive load (CSL) for each I/O standard as listed in the
table Constants for Calculating TIOOP, below.
For other capacitive loads, use the formulas below to calcu-
late an adjusted propagation delay, TIOOP1.
TIOOP1 = TIOOP + Adj + (CLOAD – CSL) * FL
Where:
Adj is selected from IOB Output Delay Adjustments
for Different Standards(1), page 40, according
to the I/O standard used
CLOAD is the capacitive load for the design
FLis the capacitance scaling factor
Delay Measurement Methodology
Standard VL(1) VH
(1)
Meas.
Point
VREF
Typ (2)
LVTTL 0 3 1.4 -
LVCMOS2 02.5 1.125 -
PCI33_3 Per PCI Spec -
PCI66_3 Per PCI Spec -
GTL VREF – 0.2 VREF + 0.2 VREF 0.80
GTL+ VREF – 0.2 VREF + 0.2 VREF 1.0
HSTL Class I VREF – 0.5 VREF + 0.5 VREF 0.75
HSTL Class III VREF – 0.5 VREF + 0.5 VREF 0.90
HSTL Class IV VREF – 0.5 VREF + 0.5 VREF 0.90
SSTL3 I and II VREF – 1.0 VREF + 1.0 VREF 1.5
SSTL2 I and II VREF 0.75 VREF + 0.75 VREF 1.25
CTT VREF – 0.2 VREF + 0.2 VREF 1.5
AGP VREF
(0.2xVCCO)
VREF +
(0.2xVCCO)
VREF Per AGP
Spec
LVDS 1.2 – 0.125 1.2 + 0.125 1.2
LVPECL 1.6 – 0.3 1.6 + 0.3 1.6
Notes:
1. Input waveform switches between VL and VH.
2. Measurements are made at VREF Typ, Maximum, and
Minimum. Worst-case values are reported.
3. I/O parameter measurements are made with the capacitance
values shown in the following table, Constants for Calculating
TIOOP. Refer to Application Note XAPP179 for appropriate
terminations.
4. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
Constants for Calculating TIOOP
Standard
CSL(1)
(pF)
FL
(ns/pF)
LVTTL Fast Slew Rate, 2 mA drive 35 0.41
LVTTL Fast Slew Rate, 4 mA drive 35 0.20
LVTTL Fast Slew Rate, 6 mA drive 35 0.13
LVTTL Fast Slew Rate, 8 mA drive 35 0.079
LVTTL Fast Slew Rate, 12 mA drive 35 0.044
LVTTL Fast Slew Rate, 16 mA drive 35 0.043
LVTTL Fast Slew Rate, 24 mA drive 35 0.033
LVTTL Slow Slew Rate, 2 mA drive 35 0.41
LVTTL Slow Slew Rate, 4 mA drive 35 0.20
LVTTL Slow Slew Rate, 6 mA drive 35 0.100
LVTTL Slow Slew Rate, 8 mA drive 35 0.086
LVTTL Slow Slew Rate, 12 mA drive 35 0.058
LVTTL Slow Slew Rate, 16 mA drive 35 0.050
LVTTL Slow Slew Rate, 24 mA drive 35 0.048
LVCMO S2 35 0.041
LVCMO S18 35 0.050
PCI 33 MHz 3.3V 10 0.050
PCI 66 MHz 3.3V 10 0.033
GTL 00.014
GTL+ 00.017
HSTL Class I 20 0.022
HSTL Class III 20 0.016
HSTL Class IV 20 0.014
SSTL2 Class I 30 0.028
SSTL2 Class II 30 0.016
SSTL3 Class I 30 0.029
SSTL3 Class II 30 0.016
CTT 20 0.035
AGP 10 0.037
Notes:
1. I/O parameter measurements are made with the capacitance
values shown above. Refer to Application Note XAPP179 for
appropriate terminations.
2. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
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Clock Distribution Switching Characteristics
TGPIO is specified for LVTTL levels. For other standards, adjust TGPIO with the values shown in I/O Standard Global Clock
Input Adjustments.
I/O Standard Global Clock Input Adjustments
Delays associated with a global clock input pad are specified for LVTTL levels. For other standards, adjust the delays by the
values shown. A delay adjusted in this way constitutes a worst-case limit.
Symbol Description
Speed Grade
Units
-7 -6
Max Max
GCLK IOB and Buffer
TGPIO Global clock pad to output 0.7 0.7 ns
TGIO Global clock buffer I input to O output 0.45 0.5 ns
Symbol Description Standard
Speed Grade
Units-7 -6
Data Input Delay Adjustments
TGPLVTTL Standard-specific global clock
input delay adjustments
LVTTL 0 0 ns
TGPLVCMOS2 LVC MOS2 0 0 ns
TGPLVCMOS18 LV CMOS18 0.2 0.2 ns
TGPLVCDS LVDS 0.38 0.38 ns
TGPLVPECL LVCPECL 0.38 0.38 ns
TGPPCI33_3 PCI, 33 MHz, 3.3V 0.08 0.08 ns
TGPPCI66_3 PCI, 66 MHz, 3.3V –0.11 –0.11 ns
TGPGTL GTL 0.37 0.37 ns
TGPGTLP GTL+ 0.37 0.37 ns
TGPHSTL HSTL 0.27 0.27 ns
TGPSSTL2 SSTL2 0.27 0.27 ns
TGPSSTL3 SSTL3 0.27 0.27 ns
TGPCTT CTT 0.33 0.33 ns
TGPAGP AGP 0.27 0.27 ns
Notes:
1. Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 41.
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Product Specification
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DLL Timing Parameters
Because of the difficulty in directly measuring many internal
timing parameters, those parameters are derived from
benchmark timing patterns. The following guidelines reflect
worst-case values across the recommended operating con-
ditions.
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were deter-
mined through statistical measurement at the package pins
using a clock mirror configuration and matched drivers.
Figure 22, page 44, provides definitions for various parame-
ters in the table below.
Symbol Description FCLKIN
Speed Grade
Units
-7 -6
Min Max Min Max
FCLKINHF Input clock frequency (CLKDLLHF) -60 320 60 275 MHz
FCLKINLF Input clock frequency (CLKDLL) -25 160 25 135 MHz
TDLLPW Input clock pulse width 25 MHz 5.0 -5.0 -ns
50 MHz 3.0 -3.0 -ns
100 MHz 2.4 -2.4 -ns
150 MHz 2.0 -2.0 -ns
200 MHz 1.8 -1.8 -ns
250 MHz 1.5 -1.5 -ns
300 MHz 1.3 -NA -
Symbol Description FCLKIN
CLKDLLHF CLKDLL
UnitsMin Max Min Max
TIPTOL Input clock period tolerance -1.0 -1.0 ns
TIJITCC Input clock jitter tolerance (cycle-to-cycle) -±150 - ± 300 ps
TLOCK Time required for DLL to acquire lock(1) > 60 MHz -20 -20 μs
50-60 MHz ---25 μs
40-50 MHz ---50 μs
30-40 MHz ---90 μs
25-30 MHz ---120 μs
TOJITCC Output jitter (cycle-to-cycle) for any DLL clock output
(2) - ± 60 - ± 60 ps
TPHIO Phase offset between CLKIN and CLKO
(3) -±100 -±100 ps
TPHOO Phase offset between clock outputs on the DLL(4) -±140 -±140 ps
TPHIOM Phase difference between CLKIN and CLKO
(5) -±160 -±160 ps
TPHOOM Phase difference between clock outputs on the DLL(6) - ± 200 - ± 200 ps
Notes:
1. Commercial operating conditions. Add 30% for Industrial operating conditions.
2. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
3. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input clock jitter.
4. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding output jitter and input clock jitter.
5. Maximum Phase Difference between CLKIN and CLKO is the sum of output jitter and phase offset between CLKIN and CLKO, or
the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
6. Maximum Phase Difference between Clock Outputs on the DLL is the sum of output jitter and phase offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
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Figure 22: Period Tolerance and Clock Jitter
Period Tolerance:
the allowed input clock period change in nanoseconds.
Output Jitter:
the difference between an ideal
reference clock edge and the actual design.
TCLKIN + T
IPTOL
_
DS001_52_090800
Actual Period
+ Jitter
+/- Jitter
+ Maximum
Phase Difference
Phase Offset and Maximum Phase Difference
+ Phase Offset
Ideal Period
1
FCLKIN
T =
CLKIN
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CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Symbol Description
Speed Grade
Units
-7 -6
Min Max Min Max
Combinatorial Delays
TILO 4-input function: F/G inputs to X/Y outputs 0.18 0.42 0.18 0.47 ns
TIF5 5-input function: F/G inputs to F5 output 0.3 0.8 0.3 0.9 ns
TIF5X 5-input function: F/G inputs to X output 0.3 0.8 0.3 0.9 ns
TIF6Y 6-input function: F/G inputs to Y output via F6 MUX 0.3 0.9 0.3 1.0 ns
TF5INY 6-input function: F5IN input to Y output 0.04 0.2 0.04 0.22 ns
TIFNCTL Incremental delay routing through transparent latch to
XQ/YQ outputs
-0.7 -0.8 ns
TBYYB BY input to YB output 0.18 0.46 0.18 0.51 ns
Sequential Delays
TCKO FF clock CLK to XQ/YQ outputs 0.3 0.9 0.3 1.0 ns
TCKLO Latch clock CLK to XQ/YQ outputs 0.3 0.9 0.3 1.0 ns
Setup/Hold Times with Respect to Clock CLK
TICK / TCKI 4-input function: F/G inputs 1.0 / 0 -1.1 / 0 -ns
TIF5CK / TCKIF5 5-input function: F/G inputs 1.4 / 0 -1.5 / 0 -ns
TF5INCK / TCKF5IN 6-input function: F5IN input 0.8 / 0 -0.8 / 0 -ns
TIF6CK / TCKIF6 6-input function: F/G inputs via F6 MUX 1.5 / 0 -1.6 / 0 -ns
TDICK / TCKDI BX/BY inputs 0.7 / 0 -0.8 / 0 -ns
TCECK / TCKCE CE input 0.7 / 0 -0.7 / 0 -ns
TRCK / TCKR SR/BY inputs (synchronous) 0.52 / 0 -0.6 / 0 -ns
Clock CLK
TCH Pulse width, High 1.3 -1.4 -ns
TCL Pulse width, Low 1.3 -1.4 -ns
Set/Reset
TRPW Pulse width, SR/BY inputs 2.1 -2.4 -ns
TRQ Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
0.3 0.9 0.3 1.0 ns
FTOG Toggle frequency (for export control) -400 -357 MHz
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CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Symbol Description
Speed Grade
Units
-7 -6
Min Max Min Max
Combinatorial Delays
TOPX F operand inputs to X via XOR -0.8 -0.8 ns
TOPXB F operand input to XB output -0.8 -0.9 ns
TOPY F operand input to Y via XOR -1.4 -1.5 ns
TOPYB F operand input to YB output -1.1 -1.3 ns
TOPCYF F operand input to COUT output -0.9 -1.0 ns
TOPGY G operand inputs to Y via XOR -0.8 -0.9 ns
TOPGYB G operand input to YB output -1.2 -1.3 ns
TOPCYG G operand input to COUT output -0.9 -1.0 ns
TBXCY BX initialization input to COUT -0.51 -0.6 ns
TCINX CIN input to X output via XOR -0.6 -0.7 ns
TCINXB CIN input to XB -0.07 -0.1 ns
TCINY CIN input to Y via XOR -0.7 -0.7 ns
TCINYB CIN input to YB -0.4 -0.5 ns
TBYP CIN input to COUT output -0.14 -0.15 ns
Multiplier Operation
TFANDXB F1/2 operand inputs to XB output via AND -0.35 -0.4 ns
TFANDYB F1/2 operand inputs to YB output via AND -0.7 -0.8 ns
TFANDCY F1/2 operand inputs to COUT output via AND -0.5 -0.6 ns
TGANDYB G1/2 operand inputs to YB output via AND -0.6 -0.7 ns
TGANDCY G1/2 operand inputs to COUT output via AND -0.3 -0.4 ns
Setup/Hold Times with Respect to Clock CLK
TCCKX / TCKCX CIN input to FFX 1.2 / 0 -1.3 / 0 -ns
TCCKY / TCKCY CIN input to FFY 1.2 / 0 -1.3 / 0 -ns
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CLB Distributed RAM Switching Characteristics
CLB Shift Register Switching Characteristics
Block RAM Switching Characteristics
Symbol Description
Speed Grade
Units
-7 -6
Min Max Min Max
Sequential Delays
TSHCKO16 Clock CLK to X/Y outputs (WE active, 16 x 1 mode) 0.6 1.5 0.6 1.7 ns
TSHCKO32 Clock CLK to X/Y outputs (WE active, 32 x 1 mode) 0.8 1.9 0.8 2.1 ns
Setup/Hold Times with Respect to Clock CLK
TAS / TAH F/G address inputs 0.42 / 0 -0.5 / 0 -ns
TDS / TDH BX/BY data inputs (DIN) 0.53 / 0 -0.6 / 0 -ns
TWS / TWH CE input (WS) 0.7 / 0 -0.8 / 0 -ns
Clock CLK
TWPH Pulse width, High 2.1 -2.4 -ns
TWPL Pulse width, Low 2.1 -2.4 -ns
TWC Clock period to meet address write cycle time 4.2 -4.8 -ns
Symbol Description
Speed Grade
Units
-7 -6
Min Max Min Max
Sequential Delays
TREG Clock CLK to X/Y outputs 1.2 2.9 1.2 3.2 ns
Setup/Hold Times with Respect to Clock CLK
TSHDICK BX/BY data inputs (DIN) 0.53 / 0 -0.6 / 0 -ns
TSHCECK CE input (WS) 0.7 / 0 -0.8 / 0 -ns
Clock CLK
TSRPH Pulse width, High 2.1 -2.4 -ns
TSRPL Pulse width, Low 2.1 -2.4 -ns
Symbol Description
Speed Grade
Units
-7 -6
Min Max Min Max
Sequential Delays
TBCKO Clock CLK to DOUT output 0.6 3.1 0.6 3.5 ns
Setup/Hold Times with Respect to Clock CLK
TBACK / TBCKA ADDR inputs 1.0 / 0 -1.1 / 0 -ns
TBDCK/ TBCKD DIN inputs 1.0 / 0 -1.1 / 0 -ns
TBECK/ TBCKE EN inputs 2.2 / 0 -2.5 / 0 -ns
TBRCK/ TBCKR RST input 2.1 / 0 -2.3 / 0 -ns
TBWCK/ TBCKW WEN input 2.0 / 0 -2.2 / 0 -ns
Clock CLK
TBPWH Pulse width, High 1.4 -1.5 -ns
TBPWL Pulse width, Low 1.4 -1.5 -ns
TBCCS CLKA -> CLKB setup time for different ports 2.7 -3.0 -ns
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TBUF Switching Characteristics
JTAG Test Access Port Switching Characteristics
Configuration Switching Characteristics
Symbol Description
Speed Grade
Units
-7 -6
Max Max
TIO IN input to OUT output 0 0 ns
TOFF TRI input to OUT output high impedance 0.1 0.11 ns
TON TRI input to valid data on OUT output 0.1 0.11 ns
Symbol Description
Speed Grade
Units
-7 -6
Min Max Min Max
Setup/Hold Times with Respect to TCK
TTAPTCK / TTCKTAP TMS and TDI setup times and hold times 4.0 / 2.0 -4.0 / 2.0 -ns
Sequential Delays
TTCKTDO Output delay from clock TCK to output TDO -11.0 -11.0 ns
FTCK TCK clock frequency -33 -33 MHz
Notes:
1. Before configuration can begin, VCCINT and VCCO Bank 2 must reach the recommended operating voltage.
Figure 23: Configuration Timing on Power-Up
DS001_12_102301
T
POR
T
PL
T
ICCK
Valid
CCLK Output or Input
M0, M1, M2
(Required)
PROGRAM
INIT
V
CC
(1)
.
Symbol Description
All Devices
UnitsMin Max
TPOR Power-on reset - 2 ms
TPL Program latency - 100 μs
TICCK CCLK output delay (Master serial
mode only)
0.5 4 μs
TPROGRAM Program pulse width 300 - ns
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Figure 24: Slave Serial Mode Timing
Figure 25: Master Serial Mode Timing
TCCH
TCCO
TCCL
TCCD
TDCC
DIN
CCLK
DOUT
(Output)
DS001_16_032300
.
Symbol Description
All Devices
UnitsMin Max
TDCC /
TCCD
CCLK
DIN setup/hold 5 / 0 - ns
TCCO DOUT - 12 ns
TCCH High time 5 - ns
TCCL Low time 5 - ns
FCC Maximum frequency - 66 MHz
Serial Data In
CCLK
(Output)
Serial DOUT
(Output)
TDSCK
TCCO
TCKDS
DS001_17_110101
.
Symbol Description
All Devices Units
Min Max
TDSCK /
TCKDS
CCLK
DIN setup/hold 5 / 0 - ns
TCCO DOUT - 12 ns
FCC Frequency tolerance with respect to
nominal
–30% +45% -
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Figure 26: Slave Parallel (SelectMAP) Mode Write Timing
Figure 27: Slave Parallel (SelectMAP) Mode Write Abort Waveforms
DS001_20_061200
CCLK
No Write Write No Write Write
DATA[7:0]
CS
WRITE
TSMDCC TSMCCD
TSMCKBY
TSMCCCS
TSMWCC
TSMCCW
TSMCSCC
BUSY
Symbol Description
All Devices
UnitsMin Max
TSMDCC /
TSMCCD
CCLK
D0-D7 setup/hold 5 / 1 - ns
TSMCSCC /
TSMCCCS
CS setup/hold 7 / 1 - ns
TSMCCW /
TSMWCC
WRITE setup/hold 7 / 1 - ns
TSMCKBY BUSY propagation delay - 12 ns
FCC Frequency - 66 MHz
FCCNH Frequency with no handshake - 50 MHz
DS001_21_032300
CCLK
CS
WRITE
Abort
DATA[7:0]
BUSY
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Revision History
Date Version Description
11/15/2001 1.0 Initial Xilinx release.
06/28/2002 1.1 Added -7 speed grade and extended DLL specs to Industrial.
11/18/2002 2.0 Added XC2S400E and XC2S600E. Added minimum specifications. Added reference to
XAPP450 for Power-On Requirements. Removed Preliminary designation.
07/09/2003 2.1 Added ICCINTQ typical values. Reduced I CCPO power-on current requirements. Relaxed
TCCPO power-on ramp requirements. Added IHSPO to describe current in hot-swap
applications. Updated TPSFD / TPHFD description to indicate use of delay element.
06/18/2008 2.3 Updated I/O measurement thresholds. Updated all modules for continuous page, figure, and
table numbering. Updated links. Synchronized all modules to v2.3.
08/09/2013 3.0 This product is obsolete/discontinued per XCN12026.
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Product Specification
© 2001–-2013 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
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Introduction
This section describes how the various pins on a
Spartan®-IIE FPGA connect within the supported
component packages, and provides device-specific thermal
characteristics. Spartan-IIE FPGAs are available in both
standard and Pb-free, RoHS versions of each package, with
the Pb-free version adding a “G” to the middle of the
package code. Except for the thermal characteristics, all
information for the standard package applies equally to the
Pb-free package.
Pin Types
Most pins on a Spartan-IIE FPGA are general-purpose,
user-defined I/O pins. There are, however, different
functional types of pins on Spartan-IIE FPGA packages, as
outlined below.
Spartan-IIE FPGA Family:
Pinout Tables
DS077-4 (v3.0) August 9, 2013 0Product Specification
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Pin Definitions
Pad Name
Dedicated
Pin Direction Description
GCK0, GCK1, GCK2,
GCK3
No Input Clock input pins that connect to Global Clock buffers or DLL
inputs. These pins become user inputs when not needed for
clocks.
DLL No Input Clock input pins that connect to DLL input or feedback clocks.
Differential clock input (N input of pair) when paired with adjacent
GCK input. Becomes a user I/O when not needed for clocks.
M0, M1, M2 Ye s Input Mode pins used to specify the configuration mode.
CCLK Ye s Input or Output The configuration Clock I/O pin. It is an input for Slave Parallel
and Slave Serial modes, and output in Master Serial mode. After
configuration, it is an input only with Don’t Care logic levels.
PROGRAM Ye s Input Initiates a configuration sequence when asserted Low.
DONE Ye s Bidirectional Indicates that configuration loading is complete, and that the
start-up sequence is in progress. The output may be open drain.
INIT No Bidirectional
(Open-drain)
When Low, indicates that the configuration memory is being
cleared. Goes High to indicate the end of initialization. Goes back
Low to indicate a CRC error. This pin becomes a user I/O after
configuration.
DOUT/BUSY No Output In Slave Parallel mode, BUSY controls the rate at which
configuration data can be loaded. It is not needed below 50 MHz.
This pin becomes a user I/O after configuration unless the Slave
Parallel port is retained.
In serial modes, DOUT provides configuration data to
downstream devices in a daisy-chain. This pin becomes a user
I/O after configuration.
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D0/DIN, D1, D2, D3,
D4, D5, D6, D7
No Input or Output In Slave Parallel mode, D0-D7 are configuration data input pins.
During readback, D0-D7 are output pins. These pins become
user I/Os after configuration unless the Slave Parallel port is
retained.
In serial modes, DIN is the single data input. This pin becomes a
user I/O after configuration.
WRITE No Input In Slave Parallel mode, the active-low Write Enable signal. This
pin becomes a user I/O after configuration unless the Slave
Parallel port is retained.
CS No Input In Slave Parallel mode, the active-low Chip Select signal. This pin
becomes a user I/O after configuration unless the Slave Parallel
port is retained.
TDI, TDO, TMS, TCK Ye s Mixed Boundary Scan Test Access Port pins (IEEE 1149.1).
VCCINT Ye s Input 1.8V power supply pins for the internal core logic.
VCCO Ye s Input Power supply pins for output drivers (1.5V, 1.8V, 2.5V, or 3.3V
subject to banking rules in the Functional Description module.
VREF No Input Input threshold reference voltage pins. Become user I/Os when
an external threshold voltage is not needed (subject to banking
rules in the Functional Description module.
GND Ye s Input Ground. All must be connected.
IRDY, TRDY No See PCI core
documentation
These signals can only be accessed when using Xilinx PCI cores.
If the cores are not used, these pins are available as user I/Os.
L#[P/N]
(e.g., L0P)
No Bidirectional Differential I/O with synchronous output. P = positive, N =
negative. The number (#) is used to associate the two pins of a
differential pair. Becomes a general user I/O when not needed for
differential signals.
L#[P/N]_Y
(e.g., L0P_Y)
No Bidirectional Differential I/O with asynchronous or synchronous output
(asynchronous output not compatible for all densities in a
package). P = positive, N = negative. The number (#) is used to
associate the two pins of a differential pair. Becomes a general
user I/O when not needed for differential signals.
L#[P/N]_YY
(e.g., L0P_YY)
No Bidirectional Differential I/O with asynchronous or synchronous output
(compatible for all densities in a package). P = positive, N =
negative. The number (#) is used to associate the two pins of a
differential pair. Becomes a general user I/O when not needed for
differential signals.
I/O No Bidirectional These pins can be configured to be input and/or output after
configuration is completed. Unused I/Os are disabled with a weak
pull-down resistor. After power-on and before configuration is
completed, these pins are either pulled up or left floating
according to the Mode pin values. See the DC and Switching
Characteristics module for power-on characteristics.
Pin Definitions (Continued)
Pad Name
Dedicated
Pin Direction Description
X XlllNX” e UG112 Xilinx web siie Package Drawing PK1697TQ144 PK1267TQG144 Package Drawing PK1667P0208 PK1237PQG208 Package Drawing PK1587FF256 PK1157FFG256 Package Drawing PK1547FG456 PK1097FGG456 Package Drawing PK1557FG676 PK1117FGG676 www.xilinx.com
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Spartan-IIE Package Pinouts
The Spartan®-IIE family of FPGAs is available in five popu-
lar, low-cost packages, including plastic quad flat packs and
fine-pitch ball grid arrays. Family members have footprint
compatibility across devices provided in the same package,
with minor exceptions due to the smaller number of I/O in
smaller devices or due to LVDS/LVPECL pin pairing. The
Spartan-IIE family is not footprint compatible with any other
FPGA family. The following package-specific pinout tables
indicate function, pin, and bank information for all devices
available in that package. The pinouts follow the pad loca-
tions around the die, starting from pin 1 on the QFP pack-
ages.
Package Overview
Ta ble 12 shows the five low-cost, space-saving production
package styles for the Spartan-IIE family.
Each package style is available in an environmentally
friendly lead-free (Pb-free) option. The Pb-free packages
include an extra ‘G’ in the package style name. For
example, the standard “TQ144” package becomes
“TQG144” when ordered as the Pb-free option. Leaded
(non-Pb-free) packages may be available for selected
devices, with the same pin-out and without the "G" in the
ordering code; contact Xilinx® sales for more information.
The mechanical dimensions of the standard and Pb-free
packages are similar, as shown in the mechanical drawings
provided in Ta b l e 13.
For additional package information, see UG112: Device
Package User Guide.
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx web site at the specified location in
Table 13.
Material Declaration Data Sheets (MDDS) are also
available on the Xilinx web site for each package.
Table 12: Spartan-IIE Family Package Options
Package Leads Type Maximum
I/O
Lead Pitch
(mm)
Footprint
Area (mm)
Height
(mm)
Mass(1)
(g)
TQ144 / TQG144 144 Thin Quad Flat Pack (TQFP) 102 0.5 22 x 22 1.60 1.4
PQ208 / PQG208 208 Plastic Quad Flat Pack (PQFP) 146 0.5 30.6 x 30.6 3.70 5.3
FT256 / FTG256 256 Fine-pitch Thin Ball Grid Array (FBGA) 182 1.0 17 x 17 1.55 1.0
FG456 / FGG456 456 Fine-pitch Ball Grid Array (FBGA) 329 1.0 23 x 23 2.60 2.2
FG676 / FGG676 676 Fine-pitch Ball Grid Array (FBGA) 514 1.0 27 x 27 2.60 3.1
Notes:
1. Package mass is ±10%.
Table 13: Xilinx Package Documentation
Package Drawing MDDS
TQ144 Package Drawing PK169_TQ144
TQG144 PK126_TQG144
PQ208 Package Drawing PK166_PQ208
PQG208 PK123_PQG208
FT256 Package Drawing PK158_FT256
FTG256 PK115_FTG256
FG456 Package Drawing PK154_FG456
FGG456 PK109_FGG456
FG676 Package Drawing PK155_FG676
FGG676 PK111_FGG676
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Product Specification
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Package Thermal Characteristics
Ta ble 14 provides the thermal characteristics for the various
Spartan-II FPGA package offerings. This information is also
available using the Thermal Query tool on xilinx.com
(www.xilinx.com/cgi-bin/thermal/thermal.pl).
The junction-to-case thermal resistance (θJC) indicates the
difference between the temperature measured on the
package body (case) and the die junction temperature per
watt of power consumption. The junction-to-board (θJB)
value similarly reports the difference between the board and
junction temperature. The junction-to-ambient (θJA) value
reports the temperature difference between the ambient
environment and the junction temperature. The θJA value is
reported at different air velocities, measured in linear feet
per minute (LFM). The “Still Air (0 LFM)” column shows the
θJA value in a system without a fan. The thermal resistance
drops with increasing air flow.
Table 14: Spartan-IIE Package Thermal Characteristics
Package Device
Junction-to-Case
(θJC)
Junction-to-
Board (θJB)
Junction-to-Ambient (θJA)
at Different Air Flows
Units
Still Air
(0 LFM) 250 LFM 500 LFM 750 LFM
TQ144
TQG144
XC2S50E 5.8 N/A 32.3 25.1 21.5 20.1 °C/Watt
XC2S100E 5.3 N/A 31.4 24.4 20.8 19.6 °C/Watt
PQ208
PQG208
XC2S50E 7.1 N/A 35.1 25.9 22.9 21.2 °C/Watt
XC2S100E 6.1 N/A 34.2 25.2 22.3 20.7 °C/Watt
XC2S150E 6.0 N/A 34.1 25.2 22.2 20.6 °C/Watt
XC2S200E 4.6 N/A 32.4 23.9 21.2 19.6 °C/Watt
XC2S300E 4.0 N/A 31.6 23.3 20.6 19.1 °C/Watt
FT256
FTG256
XC2S50E 7.3 17.8 27.4 21.6 20.4 20.0 °C/Watt
XC2S100E 5.8 15.1 25.0 19.5 18.2 17.8 °C/Watt
XC2S150E 5.7 14.8 24.8 19.3 18.0 17.6 °C/Watt
XC2S200E 3.9 11.4 21.9 16.6 15.2 14.7 °C/Watt
XC2S300E 3.2 10.1 20.8 15.6 14.2 13.7 °C/Watt
XC2S400E 2.5 8.8 19.7 14.5 13.2 12.6 °C/Watt
FG456
FGG456
XC2S100E 8.4 14.9 24.3 19.2 18.1 17.4 °C/Watt
XC2S150E 8.2 14.6 24.1 19.0 17.9 17.1 °C/Watt
XC2S200E 6.3 11.6 21.0 16.1 15.0 14.3 °C/Watt
XC2S300E 5.6 10.4 19.9 15.1 13.9 13.2 °C/Watt
XC2S400E 3.6 6.5 17.7 11.7 10.5 10.0 °C/Watt
XC2S600E 2.7 5.0 17.3 11.2 10.0 9.5 °C/Watt
FG676
FGG676
XC2S400E 4.1 7.9 15.6 11.1 9.8 9.2 °C/Watt
XC2S600E 3.4 6.9 14.5 9.9 8.6 7.9 °C/Watt
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Product Specification
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Low Voltage Differential Signals (LVDS
and LVPECL)
The Spartan-IIE family features low-voltage differential sig-
naling (LVDS and LVPECL). Each signal utilizes two pins on
the Spartan-IIE device, known as differential pin pairs. Each
differential pin pair has a Positive (P) and a Negative (N) pin.
These pairs are labeled in the following manner.
I/O, L#[P/N][-/_Y/_YY]
where
L = LVDS or LVPECL pin
# = Pin pair number
P = Positive
N = Negative
_Y = Asynchronous output allowed (device-dependent)
_YY = Asynchronous output allowed (all devices)
Synchronous or Asynchronous
I/O pins for differential signals can either be synchronous or
asynchronous, input or output. Differential signaling
requires the pins of each pair to switch simultaneously. If the
output signals driving the pins are from IOB flip-flops, they
are synchronous. If the signals driving the pins are from
internal logic, they are asynchronous, and therefore more
care must be taken that they are simultaneous. Any differ-
ential pairs can be used for synchronous input and output
signals as well as asynchronous input signals.
However, only the differential pairs with the _Y or _YY suffix
can be used for asynchronous output signals.
Asynchronous Output Pad Name Designation
Because of differences between densities, the differential
pairs that can be used for asynchronous outputs vary by
device. The pairs that are available in all densities for a
given package have the _YY suffix. These pins should be
used for differential asynchronous outputs if the design may
later move to a different density. All other differential pairs
that can be used for asynchronous outputs have the _Y suf-
fix.
To simplify the following tables, the "Pad Name" column
shows the part of the name that is common across densi-
ties. The "Pad Name" column leaves out the _Y suffix and
the "LVDS Asynchronous Output Option" column indicates
the densities that allow asynchronous outputs for LVDS or
LVPECL on the given pin.
DLL Pins
Pins labeled "I/O (DLL)" can be used as general-purpose
I/O or as inputs to the DLL. Adjacent DLL pins form a differ-
ential pair. They reside in two different banks, so if they are
outputs the VCCO level must be the same for both banks.
Each DLL pin can also be paired with the adjacent GCK
clock pin for a differential clock input. The "I/O (DLL)" pin
always becomes the N terminal when paired with GCK,
even if it is labeled "P" for its pairing with the adjacent DLL
pin.
VREF Pins
Pins labeled "I/O, VREF" can be used as either an I/O or a
VREF pin. If any I/O pin within the bank requires a VREF
input, all the VREF pins in the bank must be connected to
the same voltage. See the I/O banking rules in the Func-
tional Description module for more detail. If no pin in a
given bank requires VREF, then that bank's VREF pins can
be used as general I/O.
To simplify the following tables, the "Pad Name" column
shows the part of the name that is common across densi-
ties. When VREF is only available in limited densities, the
"Pad Name" column leaves out the VREF designation and
the "VREF Option" column indicates the densities that pro-
vide VREF on the given pin.
VCCO Banks
In the TQ144 and PQ208 packages, the eight banks have
VCCO connected together. Thus, only one VCCO is
allowed in these packages, although different VREF values
are allowed in each of the eight banks. See I/O Banking.
Available Differential Pairs According to
Package Type
Device TQ144 PQ208 FT256 FG456 FG676
XC2S50E 28 50 83 - -
XC2S100E 28 50 83 86 -
XC2S150E -50 83 114 -
XC2S200E -50 83 120 -
XC2S300E -50 83 120 -
XC2S400E - - 83 120 172
XC2S600E - - - 120 205
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Product Specification
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Pinout Tables
The following device-specific pinout tables include all pack-
ages available for each Spartan-IIE device. They follow the
pad locations around the die. In the TQ144 package, all
VCCO pins must be connected to the same voltage.
TQ144 Pinouts (XC2S50E and XC2S100E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
Option
Function Bank
GND -P1 - -
TMS -P2 - -
I/O 7P3 - -
I/O 7P4 - -
I/O, VREF
Bank 7
7P5 -All
I/O 7P6 - -
I/O, L27P 7P7 XC2S50E XC2S100E
I/O, L27N 7P8 XC2S50E -
GND -P9 - -
I/O, L26P_YY 7P10 All -
I/O, L26N_YY 7P11 All -
I/O, VREF
Bank 7, L25P
7P12 XC2S50E All
I/O, L25N 7P13 XC2S50E -
I/O 7P14 - -
I/O (IRDY) 7P15 - -
GND -P16 - -
VCCO -P17 - -
I/O (TRDY) 6P18 - -
VCCINT -P19 - -
I/O 6P20 - -
I/O, L24P 6P21 XC2S50E -
I/O, VREF
Bank 6, L24N
6P22 XC2S50E All
I/O, L23P_YY 6P23 All -
I/O, L23N_YY 6P24 All -
GND -P25 - -
I/O, L22P 6P26 XC2S50E -
I/O, L22N 6P27 XC2S50E XC2S100E
I/O 6P28 - -
I/O, VREF
Bank 6
6P29 -All
I/O 6P30 - -
I/O, L21P_YY 6P31 All -
I/O, L21N_YY 6P32 All -
M1 -P33 - -
GND -P34 - -
M0 -P35 - -
VCCO -P36 - -
M2 -P37 - -
I/O, L20N_YY 5P38 All -
I/O, L20P_YY 5P39 All -
I/O 5P40 - -
I/O, VREF
Bank 5
5P41 -All
I/O 5P42 - -
I/O, L19N_YY 5P43 All XC2S100E
I/O, L19P_YY 5P44 All -
GND -P45 - -
VCCINT -P46 - -
I/O, L18N_YY 5P47 All -
I/O, L18P_YY 5P48 All -
I/O, VREF
Bank 5
5P49 -All
I/O (DLL), L17N 5P50 - -
VCCINT -P51 - -
GCK1, I 5P52 - -
VCCO 5P53 - -
GND -P54 - -
GCK0, I 4P55 - -
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
OptionFunction Bank
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Product Specification
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I/O (DLL), L17P 4P56 - -
I/O 4P57 - -
I/O, VREF
Bank 4
4P58 -All
I/O, L16N_YY 4P59 All -
I/O, L16P_YY 4P60 All -
VCCINT -P61 - -
GND -P62 - -
I/O, L15N_YY 4P63 All -
I/O, L15P_YY 4P64 All XC2S100E
I/O 4P65 - -
I/O, VREF
Bank 4
4P66 -All
I/O 4P67 - -
I/O, L14N_YY 4P68 All -
I/O, L14P_YY 4P69 All -
GND -P70 - -
DONE 3P71 - -
VCCO -P72 - -
PROGRAM -P73 - -
I/O (INIT),
L13N_YY
3P74 All -
I/O (D7),
L13P_YY
3P75 All -
I/O 3P76 - -
I/O, VREF
Bank 3
3P77 -All
I/O 3P78 - -
I/O, L12N 3P79 XC2S50E XC2S100E
I/O (D6), L12P 3P80 XC2S50E -
GND -P81 - -
I/O (D5),
L11N_YY
3P82 All -
I/O, L11P_YY 3P83 All -
I/O 3P84 - -
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
OptionFunction Bank
I/O, VREF
Bank 3, L10N
3P85 XC2S50E All
I/O (D4), L10P 3P86 XC2S50E -
I/O 3P87 - -
VCCINT -P88 - -
I/O (TRDY) 3P89 - -
VCCO -P90 - -
GND -P91 - -
I/O (IRDY) 2P92 - -
I/O 2P93 - -
I/O (D3), L9N 2P94 XC2S50E -
I/O, VREF
Bank 2, L9P
2P95 XC2S50E All
I/O 2P96 - -
I/O, L8N_YY 2P97 All -
I/O (D2),
L8P_YY
2P98 All -
GND -P99 - -
I/O (D1), L7N 2P100 XC2S50E -
I/O, L7P 2P101 XC2S50E XC2S100E
I/O 2P102 - -
I/O, VREF
Bank 2
2P103 -All
I/O 2P104 - -
I/O (DIN, D0),
L6N_YY
2P105 All -
I/O (DOUT,
BUSY),
L6P_YY
2P106 All -
CCLK 2P107 - -
VCCO -P108 - -
TDO 2P109 - -
GND -P110 - -
TDI -P111 - -
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
OptionFunction Bank
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I/O (CS),
L5P_YY
1P112 All -
I/O (WRITE),
L5N_YY
1P113 All -
I/O 1P114 - -
I/O, VREF
Bank 1
1P115 -All
I/O 1P116 - -
I/O, L4P_YY 1P117 All XC2S100E
I/O, L4N_YY 1P118 All -
GND -P119 - -
VCCINT -P120 - -
I/O, L3P_YY 1P121 All -
I/O, L3N_YY 1P122 All -
I/O, VREF
Bank 1
1P123 -All
I/O 1P124 - -
I/O (DLL), L2P 1P125 - -
GCK2, I 1P126 - -
GND -P127 - -
VCCO -P128 - -
GCK3, I 0P129 - -
VCCINT -P130 - -
I/O (DLL), L2N 0P131 - -
I/O, VREF
Bank 0
0P132 -All
I/O, L1P_YY 0P133 All -
I/O, L1N_YY 0P134 All -
VCCINT -P135 - -
GND -P136 - -
I/O, L0P_YY 0P137 All -
I/O, L0N_YY 0P138 All XC2S100E
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
OptionFunction Bank
I/O 0P139 - -
I/O, VREF
Bank 0
0P140 -All
I/O 0P141 - -
I/O 0P142 - -
TCK -P143 - -
VCCO -P144 - -
TQ144 Differential Clock Pins
Clock Bank
P N
Pin Name Pin Name
GCK0 4P55 GCK0, I P56 I/O (DLL),
L17P
GCK1 5P52 GCK1, I P50 I/O (DLL),
L17N
GCK2 1P126 GCK2, I P125 I/O (DLL),
L2P
GCK3 0P129 GCK3, I P131 I/O (DLL),
L2N
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
OptionFunction Bank
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Product Specification
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In the PQ208 package, all VCCO pins must be connected to
the same voltage.
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
Option
Function Bank
GND -P1 - -
TMS -P2 - -
I/O 7P3 - -
I/O 7P4 -XC2S200E,
300E
I/O 7P5 - -
I/O, VREF
Bank 7,
L49P
7P6 XC2S50E,
150E, 200E,
300E
All
I/O, L49N 7P7 XC2S50E,
150E, 200E,
300E
-
I/O 7P8 - -
I/O 7P9 - -
I/O, L48P 7P10 XC2S50E,
300E
XC2S100E,
150E, 200E,
300E
I/O, L48N 7P11 XC2S50E,
300E
-
GND -P12 - -
VCCO -P13 - -
VCCINT -P14 - -
I/O,
L47P_YY
7P15 All -
I/O,
L47N_YY
7P16 All -
I/O,
L46P_YY
7P17 All -
I/O,
L46N_YY
7P18 All -
GND -P19 - -
I/O, VREF
Bank 7,
L45P
7P20 XC2S50E,
300E
All
I/O, L45N 7P21 XC2S50E,
300E
-
I/O 7P22 - -
I/O,
L44P_YY
7P23 All -
I/O (IRDY),
L44N_YY
7P24 All -
GND -P25 - -
VCCO -P26 - -
I/O (TRDY) 6P27 - -
VCCINT -P28 - -
I/O 6P29 - -
I/O, L43P 6P30 XC2S50E,
300E
-
I/O, VREF
Bank 6,
L43N
6P31 XC2S50E,
300E
All
GND -P32 - -
I/O,
L42P_YY
6P33 All -
I/O,
L42N_YY
6P34 All -
I/O,
L41P_YY
6P35 All -
I/O,
L41N_YY
6P36 All -
VCCINT -P37 - -
VCCO -P38 - -
GND -P39 - -
I/O, L40P 6P40 XC2S50E,
300E
-
I/O, L40N 6P41 XC2S50E,
300E
XC2S100E,
150E, 200E,
300E
I/O 6P42 - -
I/O 6P43 - -
I/O 6P44 - -
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
OptionFunction Bank
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I/O, VREF
Bank 6,
L39P
6P45 XC2S100E,
150E
All
I/O, L39N 6P46 XC2S100E,
150E
-
I/O 6P47 -XC2S200E,
300E
I/O,
L38P_YY
6P48 All -
I/O,
L38N_YY
6P49 All -
M1 -P50 - -
GND -P51 - -
M0 -P52 - -
VCCO -P53 - -
M2 -P54 - -
I/O,
L37N_YY
5P55 All -
I/O,
L37P_YY
5P56 All -
I/O 5P57 -XC2S200E,
300E
I/O 5P58 - -
I/O, VREF
Bank 5,
L36N_YY
5P59 All All
I/O,
L36P_YY
5P60 All -
I/O, L35N 5P61 XC2S50E,
100E, 300E
-
I/O, L35P 5P62 XC2S50E,
100E, 300E
-
I/O, L34N 5P63 XC2S50E,
100E, 200E,
300E
XC2S100E,
150E, 200E,
300E
I/O, L34P 5P64 XC2S50E,
100E, 200E,
300E
-
GND -P65 - -
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
OptionFunction Bank
VCCO -P66 - -
VCCINT -P67 - -
I/O, L33N 5P68 XC2S50E,
100E, 200E,
300E
-
I/O, L33P 5P69 XC2S50E,
100E, 200E,
300E
-
I/O 5P70 - -
I/O, L32N 5P71 XC2S100E,
150E
-
GND -P72 - -
I/O, VREF
Bank 5,
L32P
5P73 XC2S100E,
150E
All
I/O 5P74 - -
I/O (DLL),
L31N
5P75 - -
VCCINT -P76 - -
GCK1, I 5P77 - -
VCCO -P78 - -
GND -P79 - -
GCK0, I 4P80 - -
I/O (DLL),
L31P
4P81 - -
I/O 4P82 - -
I/O, L30N 4P83 XC2S50E,
200E, 300E
-
I/O, VREF
Bank 4,
L30P
4P84 XC2S50E,
200E, 300E
All
GND -P85 - -
I/O, L29N 4P86 XC2S50E,
200E, 300E
-
I/O, L29P 4P87 XC2S50E,
200E, 300E
-
I/O, L28N 4P88 XC2S50E,
100E, 200E,
300E
-
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
OptionFunction Bank
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Product Specification
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I/O, L28P 4P89 XC2S50E,
100E, 200E,
300E
-
VCCINT -P90 - -
VCCO -P91 - -
GND -P92 - -
I/O, L27N 4P93 XC2S50E,
100E, 200E,
300E
-
I/O, L27P 4P94 XC2S50E,
100E, 200E,
300E
XC2S100E,
150E, 200E,
300E
I/O 4P95 - -
I/O 4P96 - -
I/O,
L26N_YY
4P97 All -
I/O, VREF
Bank 4,
L26P_YY
4P98 All All
I/O 4P99 - -
I/O 4P100 -XC2S200E,
300E
I/O,
L25N_YY
4P101 All -
I/O,
L25P_YY
4P102 All -
GND -P103 - -
DONE 3P104 - -
VCCO -P105 - -
PROGRAM -P106 - -
I/O (INIT),
L24N_YY
3P107 All -
I/O (D7),
L24P_YY
3P108 All -
I/O 3P109 -XC2S200E,
300E
I/O 3P110 - -
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
OptionFunction Bank
I/O, VREF
Bank 3,
L23N
3P111 XC2S50E,
150E, 200E,
300E
All
I/O, L23P 3P112 XC2S50E,
150E, 200E,
300E
-
I/O 3P113 - -
I/O 3P114 - -
I/O, L22N 3P115 XC2S50E,
300E
XC2S100E,
150E, 200E,
300E
I/O (D6),
L22P
3P116 XC2S50E,
300E
-
GND -P117 - -
VCCO -P118 - -
VCCINT -P119 - -
I/O (D5),
L21N_YY
3P120 All -
I/O,
L21P_YY
3P121 All -
I/O,
L20N_YY
3P122 All -
I/O,
L20P_YY
3P123 All -
GND -P124 - -
I/O, VREF
Bank 3,
L19N
3P125 XC2S50E,
300E
All
I/O (D4),
L19P
3P126 XC2S50E,
300E
-
I/O 3P127 - -
VCCINT -P128 - -
I/O (TRDY) 3P129 - -
VCCO -P130 - -
GND -P131 - -
I/O (IRDY),
L18N_YY
2P132 All -
I/O,
L18P_YY
2P133 All -
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
OptionFunction Bank
f: XILINX‘" www.xilinx.com
64 www.xilinx.com DS077-4 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O 2P134 - -
I/O (D3),
L17N
2P135 XC2S50E,
300E
-
I/O, VREF
Bank 2,
L17P
2P136 XC2S50E,
300E
All
GND -P137 - -
I/O,
L16N_YY
2P138 All -
I/O,
L16P_YY
2P139 All -
I/O,
L15N_YY
2P140 All -
I/O (D2),
L15P_YY
2P141 All -
VCCINT -P142 - -
VCCO -P143 - -
GND -P144 - -
I/O (D1),
L14N
2P145 XC2S50E,
300E
-
I/O, L14P 2P146 XC2S50E,
300E
XC2S100E,
150E, 200E,
300E
I/O 2P147 - -
I/O 2P148 - -
I/O 2P149 - -
I/O, VREF
Bank 2,
L13N
2P150 XC2S100E,
150E
All
I/O, L13P 2P151 XC2S100E,
150E
-
I/O 2P152 -XC2S200E,
300E
I/O (DIN,
D0),
L12N_YY
2P153 All -
I/O (DOUT,
BUSY),
L12P_YY
2P154 All -
CCLK 2P155 - -
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
OptionFunction Bank
VCCO -P156 - -
TDO 2P157 - -
GND -P158 - -
TDI -P159 - -
I/O (CS),
L11P_YY
1P160 All -
I/O
(WRITE),
L11N_YY
1P161 All -
I/O 1P162 -XC2S200E,
300E
I/O 1P163 - -
I/O, VREF
Bank 1,
L10P_YY
1P164 All All
I/O,
L10N_YY
1P165 All -
I/O 1P166 - -
I/O 1P167 - -
I/O, L9P 1P168 XC2S50E,
100E, 200E,
300E
XC2S100E,
150E, 200E,
300E
I/O, L9N 1P169 XC2S50E,
100E, 200E,
300E
-
GND -P170 - -
VCCO -P171 - -
VCCINT -P172 - -
I/O, L8P 1P173 XC2S50E,
100E, 200E,
300E
-
I/O, L8N 1P174 XC2S50E,
100E, 200E,
300E
-
I/O, L7P 1P175 XC2S50E,
200E, 300E
-
I/O, L7N 1P176 XC2S50E,
200E, 300E
-
GND -P177 - -
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
OptionFunction Bank
XXILINX“ www.xilinx.com
DS077-4 (v3.0) August 9, 2013 www.xilinx.com 65
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O, VREF
Bank 1, L6P
1P178 XC2S50E,
200E, 300E
All
I/O, L6N 1P179 XC2S50E,
200E, 300E
-
I/O 1P180 - -
I/O (DLL),
L5P
1P181 - -
GCK2, I 1P182 - -
GND -P183 - -
VCCO -P184 - -
GCK3, I 0P185 - -
VCCINT -P186 - -
I/O (DLL),
L5N
0P187 - -
I/O, L4P 0P188 XC2S50E,
200E, 300E
-
I/O, VREF
Bank 0, L4N
0P189 XC2S50E,
200E, 300E
All
GND -P190 - -
I/O, L3P 0P191 XC2S50E,
200E, 300E
-
I/O, L3N 0P192 XC2S50E,
200E, 300E
-
I/O, L2P 0P193 XC2S50E,
100E, 200E,
300E
-
I/O, L2N 0P194 XC2S50E,
100E, 200E,
300E
-
VCCINT -P195 - -
VCCO -P196 - -
GND -P197 - -
I/O, L1P 0P198 XC2S50E,
100E, 200E,
300E
-
I/O, L1N 0P199 XC2S50E,
100E, 200E,
300E
XC2S100E,
150E, 200E,
300E
I/O 0P200 - -
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)